Good day!
In my design I am using Tiva MCU, and peripherial is connected via CAN bus. Recently I realized, that my design causing errors on the bus, and after some investigation I see that:
1. When system clock is configured as 80MHz, the actual CAN module clock become 66.7MHz, and after bit timing configuration I got clock error of 0.5%, as there no accurate time quanta can be derived from 66.7MHz.
2. When system clock is configured as 66.7MHz i got even more errors, and it looks like in this case CAN module clock is unstable.
3. At 50MHz system clock everething works fine, but I got about 40% decreased system performance.
Of course, CAN will function perfect at 80MHz clock, as time quanta of 50ns is the most comfortable for 250kbit operation.
BTW, automatic bit timing configuration from TivaWare produces results that is not fully confoming to CAN bus guidelining, as sampling point is recommended to be set up at 75% of bit time, but CANBitRateSet function calculates sampling point at 50% of bit time.