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TM4C123FH6PM: Unable to use CAN with 80 or 66.7 MHz clock

Part Number: TM4C123FH6PM

Good day!

In my design I am using Tiva MCU, and peripherial is connected via CAN bus. Recently I realized, that my design causing errors on the bus, and after some investigation I see that:

1. When system clock is configured as 80MHz, the actual CAN module clock become 66.7MHz, and after bit timing configuration I got clock error of 0.5%, as there no accurate time quanta can be derived from 66.7MHz.

2. When system clock is configured as 66.7MHz i got even more errors, and it looks like in this case CAN module clock is unstable.

3. At 50MHz system clock everething works fine, but I got about 40% decreased system performance.

Of course, CAN will function perfect at 80MHz clock, as time quanta of 50ns is the most comfortable for 250kbit operation.

BTW, automatic bit timing configuration from TivaWare produces results that is not fully confoming to CAN bus guidelining, as sampling point is recommended to be set up at 75% of bit time, but CANBitRateSet function calculates sampling point at 50% of bit time.

  • Hi Oleg,

    Can you show the code how you configure the System clock for 80MHz and how you initialize the CAN module?
  • Hello!

    Clock initialization:

    /*
    SysCtlClockSet(SYSCTL_SYSDIV_2 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ); uint32_t Clk = SysCtlClockGet(); // Clk = 80000000 SysCtlClockSet(SYSCTL_SYSDIV_3 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ); uint32_t Clk = SysCtlClockGet(); // Clk = 66666666 */ SysCtlClockSet(SYSCTL_SYSDIV_4 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN | SYSCTL_XTAL_16MHZ); uint32_t Clk = SysCtlClockGet(); // Clk = 50000000

    CAN initialization:

    CANInit(CANBase);
    uint32_t Clk = SysCtlClockGet();
    
    // This works only at 50MHz system clock
    // At 80MHz this setting causes the CAN frame is 20% longer in time, seen by scope.
    // At 66.7 MHz system clock the errors almost completely blocking communication, the frame length is unstable
    //CANBitRateSet(CANBase, Clk, 250000); 
    
    // This works at 80MHz, but causes errors at bus as bit timing has 0.5% error.
    // I can communicate with other devices, but when I connect CAN bus monitor to the bus (I have PEAKCAN and VS-COM),
    // it starts generating error frames.
    //CANBitRateSet(CANBase, 66666666, 250000);
    
    // This is the best setting for 50MHz system clock
    tCANBitClkParms Params = {7, 2, 0, 20};
    CANBitTimingSet(CANBase, &Params);
    
    

  • Hi,
    I see some issue with your 80MHz setting. You wrote:

    /* SysCtlClockSet(SYSCTL_SYSDIV_2 | SYSCTL_USE_PLL | SYSCTL_OSC_MAIN |
    SYSCTL_XTAL_16MHZ);
    uint32_t Clk = SysCtlClockGet(); // Clk = 80000000

    However, the PLL VCO output is 200MHz. If you divide 200MHz by 2 you will get 100MHz. This is out of the spec. You should use SYSCTL_SYSDIV_2_5. This will divide 200MHz by 2.5 to give you 80MHz.
  • Thanx! It works.