Seemingly datasheet makes an incorrect statement that edge count (capture) mode starts when enable bit is set. I noticed this issue some time ago and added Tivaware capture bit set define TnMR in the timer configuration. However the same section omits any comment of TnCMR bit must be cleared even though POR defaults 0x0, Tivaware define sets TnCMR (0x00000004) anyone adds that to HWREG call will not get the intended resutls. Datasheet subject order has edge count prior to edge time mode. Yet define (TIMER_TAMR_TACMR) defaults timer for edge time mode.
That issue is not obvious by reading datasheet GPTM analysis. Tivaware omits distinction (hw_timer.h) defines to properly set the two capture modes for Edge or Time via TnCBR bits in the GPTMTnMR register. The GPTMCFG register does not set EDGE capture mode default, a foot note bottom of GPTMTnMR states the mode is set in GPTMCFG. Yet GPTMCFG only sets the timer spilt points and has no affiliation how GPTMTnMR bits default 0x0 reserved.
The entire subject of CCP capture mode could easily be rectified by adding a separate define for each mode (Edge/Time) as it relates to HWREG calls to symbolically set register bits.
13.3.3.3 Input Edge-Count Mode
In Edge-Count mode, the timer is configured as a 24-bit up- or down-counter including the optional prescaler with the upper count value stored in the GPTM Timer n Prescale (GPTMTnPR) register and the lower bits in the GPTMTnR register. In this mode, the timer is capable of capturing three types of events: rising edge, falling edge, or both. To place the timer in Edge-Count mode, the TnCMR bit of the GPTMTnMR register must be cleared. The type of edge that the timer counts is determined by the TnEVENT fields of the GPTMCTL register. During initialization in down-count mode, the GPTMTnMATCHR and GPTMTnPMR registers are configured so that the difference between the value in the GPTMTnILR and GPTMTnPR registers and the GPTMTnMATCHR and GPTMTnPMR registers equals the number of edge events that must be counted. In up-count mode, the timer counts from 0x0 to the value in the GPTMTnMATCHR and GPTMTnPMR registers.
Note that when executing an up-count, that the value of GPTMTnPR and GPTMTnILR must be greater than the value of GPTMTnPMR and GPTMTnMATCHR. Table 13-7 on page 961 shows the values
that are loaded into the timer registers when the timer is enabled.
When software writes the TnEN bit in the GPTM Control (GPTMCTL) register, the timer is enabled for event capture.
GPTMTnMR REG2, REG3:
1:0 TnMR RW 0x0 GPTM Timer B Mode
The TnMR values are defined as follows:
Value Description
0x0 Reserved
0x1 One-Shot Timer mode
0x2 Periodic Timer mode
0x3 Capture mode
2 GPTM Timer B Capture Mode
The TnCMR values are defined as follows:
Value Description
0 Edge-Count mode
1 Edge-Time mode
#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode (0x00000000)
#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode (0x00000000)
#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
