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RM46L852: Selectively suppressing mibSPI RX overrun

dduncan
Intellectual 315 points
Part Number: RM46L852

I'm trying to leave RX Overrun interrupts enabled and simply ignore the return data from the first transfer group that goes out.  In mibspiGroupNotification(), if I do the following then no RX overrun occurs:

uint16_t dummy_value;
(void)mibspiGetData(mibspi, group, &dummy_value);

However, if I do this instead I still get the RX overrun:

mibspi->FLG |= 0x0100U;

(Or same thing with 0xFFFFU.)

What am I missing?  The technical reference seems to indicate that this should accomplish the same thing.  I saw the RXEMPTY-related errata, but that seems to not at all be relevant here.  Thanks!

  • 0
    TI__Mastermind 21425 points
    Hello,
    Try with clearing (writing 1) the RXOVRNINTFLG flag in SPIFLG register.

    Best regards,
    Miro
  • 0 in reply to Miro
    Intellectual 315 points

    Thanks for the quick response.  I still get the RX overruns doing this; any other ideas?

  • 0 in reply to dduncan
    TI__Mastermind 21425 points
    Hello,
    Could you attache your project, so I can debug this scenario?

    Best regards,
    Miro
  • 0 in reply to Miro
    Intellectual 315 points
    I can't include the actual project, but I made up an example project that I'll try to send you directly. The key code is in mibspiGroupNotification() in notification.c and reflects the thread thus far.
  • 0 in reply to dduncan
    TI__Mastermind 21425 points
    OK, thanks!
  • 0 in reply to Miro
    TI__Mastermind 21425 points
    Hello,
    After first transmit, only TG completed interrupt is generated. If you try second transmit while leaving data in RX Ram, then RX overrun is generated (if enabled) - RXOVR bit in Multi-Buffer Receive Buffer Register (RXRAM) is set and RXOVRNINTFLG as well. You should read data field RXDATA to clear RXOVR bit. Clearing RXOVRNINTFLG does not clear RXOVR.

    Best regards,
    Miro
  • 0 in reply to Miro
    Intellectual 315 points
    From the RXRAM description table (table 27-57 of SPNU514C, Mar 2018):
    Write-clearing the RXINTFLG bit before reading RXDATA indicates the received data is being ignored. Conversely, RXINTFLG can be cleared by reading the RXDATA field of RXRAM (or the entire register).

    Perhaps I'm missing something, or that first sentence is actually only relevant when not in multi-buffer mode? In any case, I can read a dummy value. But since the SPI documentation seems overly difficult, particularly as it relates to SPI vs. mibSPI, I thought asking the question could end up being useful to others.

    Thanks for taking a look.
  • 0 in reply to dduncan
    TI__Guru**** 196996 points
    Hello Dduncan,

    In multi-buffer mode, if a particular RXRAM location is written by the MibSPI sequencer logic after the completion of a new transfer when that location already contains valid data, the RX_OVR bit will be set to 1 while the data is being written. The RXOVRN_BUF_ADDR register captures the address of the RXRAM location for which a receiver overrun condition occurred.

    Please try different buff mode of Multi-buffer RAM Transmit Data Register (TXRAM).