CCS/TMS570LC4357: Issue with uC/OS-III Run in another location at 0x00200100

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Tool/software: Code Composer Studio

I’m Arun,

    Working uC/OS-III with TMS570LC4357 (HALCoGen). i Downloaded the example project in https://www.micrium.com/download/tms570lc43xhdk_os3/ . Generally uC/OS-II run in Vector address 0x00000000 and FLASH0 address 0x00000020 is working fine. But if i changed vector location 0x00200100 and FLASH1 address 0x00200120 is not working. When i flash the code using CCS, Its directly running in location 0x00200100 and its working only first time, after restart its not working(I think its not stating properly). CCS debug mode also not working.. Below i attached my "sys_link.cmd" file and "sys_invecs.asm" file.  Please help me to run the code in 0x00200120 location? What are the changes i need to do for this in “sys_link.cmd” file and “HL_sys_intvecs.asm”???

//uC/OS-III "sys_link.cmd" file 


--retain="*(.intvecs)"     // Linker Settings     


MEMORY                          // Memory Map 
{

/*    VECTORS (X)  : origin=0x00000000 length=0x00000020
    FLASH0  (RX) : origin=0x00000020 length=0x001FFFE0
    FLASH1  (RX) : origin=0x00200000 length=0x00200000
    STACKS  (RW) : origin=0x08000000 length=0x00000700
    RAM     (RW) : origin=0x08000700 length=0x0007f900
*/
        VECTORS (X)  : origin=0x00200100 length=0x00000020
//    FLASH0  (RX) : origin=0x00000020 length=0x001FFFE0
    FLASH1  (RX) : origin=0x00200120 length=0x001FFFDF
    STACKS  (RW) : origin=0x08000000 length=0x00001500
    RAM     (RW) : origin=0x08001500 length=0x0007eb00
}


SECTIONS   //Section Configuration 
{
    .intvecs : {} > VECTORS
    .text   align(32) : {} >  FLASH1
    .const  align(32) : {} >  FLASH1
    .cinit  align(32) : {} >  FLASH1
    .pinit  align(32) : {} >  FLASH1
    .bss     : {} > RAM
    .data    : {} > RAM
    .sysmem  : {} > RAM
	
    FEE_TEXT_SECTION  : {} >  FLASH1
    FEE_CONST_SECTION : {} >  FLASH1
    FEE_DATA_SECTION  : {} > RAM
}

___________________________________________________________

; uC/OS-III "sys_invec.asm" file

 .sect ".intvecs"
    .arm

;-------------------------------------------------------------------------------
; import reference for interrupt routines

    .ref _c_int00
    .ref OS_CPU_ARM_ExceptUndefInstrHndlr
    .ref OS_CPU_ARM_ExceptSwiHndlr
    .ref OS_CPU_ARM_ExceptPrefetchAbortHndlr
    .ref OS_CPU_ARM_ExceptDataAbortHndlr
    .ref OS_CPU_ARM_ExceptIrqHndlr
    .ref phantomInterrupt
    .def resetEntry

;-------------------------------------------------------------------------------
; interrupt vectors

resetEntry
        b   _c_int00
        b   OS_CPU_ARM_ExceptUndefInstrHndlr
        b   OS_CPU_ARM_ExceptSwiHndlr
        b   OS_CPU_ARM_ExceptPrefetchAbortHndlr
        b   OS_CPU_ARM_ExceptDataAbortHndlr
        b   phantomInterrupt
        b   OS_CPU_ARM_ExceptIrqHndlr
        ldr pc,[pc,#-0x1b0]

    
;-------------------------------------------------------------------------------

Thanks in advance

Regards

Arun