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RM48L952: How to know how many quadrants are used by a slave (PCR)?

Part Number: RM48L952

Hello,

In the RM48 TRM (spnu503c) page 188 it is explained that in the PCR control registers there is 1 bit for each quadrant for PS0-PS7 ...
It seems to me like the amount of quadrants used relates to the frame size (memory) of the peripheral.
All 4 quadrants means 1kByte memory
2 quadrants means 512 Bytes
1 quadrant means 256 Bytes.

When I look at page 103 I find that both MibSPI3 and SPI4 belong to PS[1]. Each has 512 Bytes of memory.
It seems to me then that they each use 2 quadrants. From page 188 I conclude that one must use quadrant 0&1 and therefore can be controlled by the Q0 bit. The other must use quadrant 2&3 and must be controlled by the Q2 bit.
Let's say I want to powerdown SPI4 and keep MibSPI5, how must I configure PSPWRDWNSET0?
PS[7-0]QUAD[3-0]PWRDWNSET = 0x00000010;

or

PS[7-0]QUAD[3-0]PWRDWNSET = 0x00000040;
?
I am assuming it has a relation to the frame addresses.

  • Hello Coster,

    Each peripheral select (PS, Table 6-20 of RM48 datasheet) addresses a 1KB region. The region is divided into four quadrants [3 - 0], with each quadrant being 256 bytes.

    MibSPI3 registers are in the two quadrants of PS1 from 0xFFF7_F800 to 0xFFF7_F9FF

    SPI4 registers are in the other two quadrants of PS1 from 0xFFF7_FA00 to 0xFFF7_FBFF

    The controls for the four quadrants of PS1 are in the register PSPWRDWNSET0/CLR0 register bits 7 to 4. The clocks to MibSPI3 are controlled by bit 4 and the clocks to SPI4 are controlled by bit 6. Bits 5 and 7 are unused, and will read as zeros.

    To powerdown SPI4: set bit 6 of  PSPWRDWNSET0 register

    To power on  MibSPI3: set bit 4 of PSPWRDWNCLR0 register

  • Thanks QJ,

    Is it correct to assume that bits 7-4 are Q3-Q0 respectively and that the region with the lowest address (MibSPI3 in this case) corresponds with Q1/Q0?
  • Hello Coster,

    Your understanding is correct.