TM4C1294NCPDT: I2C in slave mode

Briceag Cosmin

Part Number: TM4C1294NCPDT

Hello,

I have a question regarding the I2C configuration in slave mode.

Once the master triggered the START condition we get I2C_SLAVE_INT_START, right ?

Once the master placed the slave address on I2C bus along with the operation bit (read/write), are we able to read that byte from I2C_O_SDR using I2C_SLAVE_INT_DATA ? If not, where is it placed ?

Let's suppose we have the following use case:

START->ADDRESS[0][A]->[REG_MSB][A][REG_LSB][A]->RESTART->ADDRESS[1][A]........Start generating clock and shift slave data out.......[NAK]->STOP

From slave's point of view, once the RESTART condition was triggered, how is it announced to place data in register to be shifted out, will we get any interrupt for that transaction ?

over 6 years ago

0 Charles Tsai over 6 years ago

TI__Guru**** 191886 points

Briceag Cosmin said:

Once the master triggered the START condition we get I2C_SLAVE_INT_START, right ?

Yes, since you enable the interrupt generation for detection the START condition, the slave interrupt is generated upon detecting the START from the master.

Briceag Cosmin said:

START->ADDRESS[0][A]->[REG_MSB][A][REG_LSB][A]->RESTART->ADDRESS[1][A]........Start generating clock and shift slave data out.......[NAK]->STOP

From slave's point of view, once the RESTART condition was triggered, how is it announced to place data in register to be shifted out, will we get any interrupt for that transaction ?

Please see below flowchart. After the TREQ bit is set you need to writ the data for the slave to transmit the data back to the master.