Good day everyone.
I have ran into a problem where I don't get link for around 90 seconds with crossover cable on 100mbit full duplex settings.
Is it normal for it to take this long? I am using robust MDI-X as without it I don't get link at all at these settings.
If I use auto negotiation (and normal MDI-X, not robust) then everything works within a second. It's just this particular setting that is causing me trouble.
I am using internal PHY.
This is how I configure ethernet hardware:
// Enable and reset the Ethernet SysCtlPeripheralEnable(SYSCTL_PERIPH_EMAC0); SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0); SysCtlPeripheralReset(SYSCTL_PERIPH_EMAC0); SysCtlPeripheralReset(SYSCTL_PERIPH_EPHY0);
// Wait for the MAC to be ready while (!SysCtlPeripheralReady(SYSCTL_PERIPH_EMAC0));
// Stop transmitting on the line EMACPHYConfigSet(EMAC0_BASE, EMAC_PHY_INT_HOLD);
// Enable PHY SysCtlPeripheralEnable(SYSCTL_PERIPH_EPHY0);
// Wait for the PHY to be ready while (!SysCtlPeripheralReady(SYSCTL_PERIPH_EPHY0));
// Set speed and duplex settings EMACPHYConfigSet(EMAC0_BASE, EMAC_PHY_FORCE_100B_T_FULL_DUPLEX | EMAC_PHY_INT_ROBUST_MDIX | EMAC_PHY_INT_MDIX_EN); EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_BMCR, EPHY_BMCR_DUPLEXM | EPHY_BMCR_SPEED);
// Set configuration DONE EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_CFG1, EPHY_CFG1_DONE);
// reset EMAC EMACReset(EMAC0_BASE);
// init EMAC EMACInit(EMAC0_BASE, ADN_SYS_CORE_FREQ, (EMAC_BCONFIG_FIXED_BURST | EMAC_BCONFIG_PRIORITY_FIXED), 1, 1, 0);
// configure EMAC EMACConfigSet(EMAC0_BASE, (EMAC_CONFIG_FULL_DUPLEX | EMAC_CONFIG_100MBPS | EMAC_CONFIG_CHECKSUM_OFFLOAD | EMAC_CONFIG_USE_MACADDR0 | EMAC_CONFIG_STRIP_CRC), (EMAC_MODE_RX_STORE_FORWARD | EMAC_MODE_TX_STORE_FORWARD | EMAC_MODE_RX_FLUSH_DISABLE), 0); EMACAddrSet(EMAC0_BASE, 0, psNetif->hwaddr); /* Initialize the DMA descriptors. */ InitDMADescriptors(); /* Clear any stray PHY interrupts that may be set. */ ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1); ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR2); /* Configure and enable the link status change interrupt in the PHY. */ ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_SCR); ui16Val |= (EPHY_SCR_INTEN_EXT | EPHY_SCR_INTOE_EXT); EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_SCR, ui16Val); EMACPHYWrite(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1, (EPHY_MISR1_LINKSTATEN | EPHY_MISR1_SPEEDEN | EPHY_MISR1_DUPLEXMEN | EPHY_MISR1_ANCEN)); /* Read the PHY interrupt status to clear any stray events. */ ui16Val = EMACPHYRead(EMAC0_BASE, PHY_PHYS_ADDR, EPHY_MISR1); /** * Set MAC filtering options. We receive all broadcast and mui32ticast * packets along with those addressed specifically for us. */ EMACFrameFilterSet(EMAC0_BASE, (EMAC_FRMFILTER_HASH_AND_PERFECT | EMAC_FRMFILTER_PASS_MULTICAST)); // IMPORTANT on TM4C129!!! // Disable all the MMC interrupts as these are enabled by default at reset. HWREG(EMAC0_BASE + EMAC_O_MMCRXIM) = 0xFFFFFFFF; HWREG(EMAC0_BASE + EMAC_O_MMCTXIM) = 0xFFFFFFFF; /* Clear any pending MAC interrupts. */ EMACIntClear(EMAC0_BASE, MAP_EMACIntStatus(EMAC0_BASE, false)); EMACTxEnable(EMAC0_BASE); EMACRxEnable(EMAC0_BASE); // reenable MAC interrupts after configuring EMAC IntEnable(INT_EMAC0); /* Enable the Ethernet RX and TX interrupt source. */ EMACIntEnable(EMAC0_BASE, (EMAC_INT_RECEIVE | EMAC_INT_TRANSMIT | EMAC_INT_TX_STOPPED | EMAC_INT_RX_NO_BUFFER | EMAC_INT_RX_STOPPED | EMAC_INT_PHY));
