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TM4C129ENCPDT: SDRAM compatibility

Peter Johansen
Intellectual 935 points
Part Number: TM4C129ENCPDT

In a new production batch we have seen the SDRAM AS4C32M16SB-7TIN from Alliance Memory fails with the TM4C129 processor. Previously we have been using the MT48LC32M16A2TG from Micron but that device is now obsolete and the direct replacement should be the above device from Alliance according to Digikey.

The device only fails in heavy SDRAM access, so a simple test does not show failures. We have been running the PCB layout for a long time without problems. Processor speed is 120MHz and running with the standard Tivaware setup.

We found some old Micron SDRAMs and the boards worked again.

We will now try the IS42S16320D as mentioned in the tidu893a.pdf and tidres6.pdf BOM.

As it requires a lot of work to identify the root course for the differences, have anyone seen similar behavior or give a good explanation ?

  • 0
    TI__Guru 72500 points
    I have not seen any posts on this forum of anyone else seeing this issue, but do not know if anyone else has tried using the AS4C32M16SB from Alliance Memory.
  • 0 in reply to Bob Crosby
    Intellectual 935 points
    It seems that by running the EPI drive strength set up twice solves the problem of using the 2 new SDRAMS. The code change is inspired by the code example in C:\ti\TivaWare_C_Series-2.1.4.178\examples\peripherals\lcd\sdram.c and having the comment:

    // Workaround - call these APIs again for to ensure that the correct
    // drive strength is selected.

    Is this behavior documented in an errata or anywhere else ?
  • 0 in reply to Peter Johansen
    Intellectual 935 points

    Additional to double programming of register findings it seems strange that the Tivaware execution of the EPI setting end up with all drive bits set, 2mA,4mA and 8mA, as in the users guide in the 4mA drive description (GPIODR4) it is mentioned that 'Setting a bit in either the GPIODR2 register or the GPIODR8 register clears the corresponding 4-mA enable bit. The change is effective on the next clock cycle.' See attached CCS screen dump. It should only be one of the drive bits that should be set and the other bits cleared. In the Screen shot it's the port A bits 6 and 7 that are used for EPI.

  • 0 in reply to Peter Johansen
    Intellectual 935 points
    Have anyone else seen this behavior or found documentation explaining what we see ?