CCS/TMS570LS1227: MibSpi1 as slave mode receive 280069 Spi(Master mode) digital data, MibSpi1 Rx Ram Buff Receive data error

Part Number: TMS570LS1227

Tool/software: Code Composer Studio

Hi QJ Wang

We have a problem, MibSpi1 ccan receive data, but the received data is garbled,

eg. SPI Mast continuous transmission 0x1111,0x2222; but MibSpi received datat is 0x2222,0x4444;Or other data.

Use an oscilloscope to observe the SOMI signal, compared to the clock signal is 0x1111,0x2222;

we have check the polarity, phase, clock, matching master setting looks no problem. We have try 4 ways Clocking Modes

if we choose transfer group length 1, mibSpi receive correct. However we choose choose transfer group length >2, it receive data error.

code：spiRecFlag = mibspiGetData(mibspiREG1,0,&ReciveBuff[0]);

yellow:SPICLK; Green: SPISOMI; blue:SPISIOM;

the SPISOMI signal why level is uncertain, sometimes high, sometimes low?

Hello,

How many SPI pins are used to interface the 280069 SPI master? Do you use blue wires to connect two devices or they are on the same PCB board? If they are on different PCB board, can you lower your SPI speed for example 1mbps?

Hi QJ Wang
we use 4 pin (SPICLK; SPISOMI; SPISIOM;SPICS) mode.
What is the difference between the SPI_CS and SPIENA pin?
Can use slave SPIENA connect with master SPI_CS?

Hello,

SPI_CS is used by master to select a slave. In multi-buffer SPI mode, SPI slave is triggered by CS signal. SPI_ENA is used by slave to delay the the generation of the clock signal supplied by the master. A high SPI_ENA signal tells the master to hold the clock signal, and the low SPI_ENA signal tells the master that it is ready to receive data and allows the master to drive the clock stream.

You can not connect master SPI_CS to slave SPI_ENA.

Hi QJ wang
Does it mean that the multi-buffer SPI mode must be used with the SPI_ENA pin?
Is there a detailed timing diagram as slave if it use the SPI_ENA Pin function?

Hi,

The SPI_ENA is optional, not required. When the SPIENA signal is disabled, the SPIENA pin is ignored in master mode, and not driven as part of the SPI transaction in slave mode. You can use 3pin, 4-pin, and 5-pin modes for both SPI and MibSPI.

When the MibSPI is in 3-pin or 4-pin with SPIENA mode, just one Transfer Group can be triggered and it is restricted to Transfer Group 0 (TG0).

Hi QJ Wang
We use 28069 SPI as master, the SPI_ENA signal is not used. The master need pull down the SPI_CS, and then wait 6 VCLK cycles, and then master sending the clock. is right?
our have other problem.
Enable break point during debugging, have one GPIO output PWM (use Enhanced Pulse Width Modulator Module achieve), when software stop running, the GPIO stop output PWM too.
Is there a way to make the PWM output unaffected by the breakpoint?

Thank you.

Hello,

You are correct. In slave mode, the chip select is used to trigger the data transfer between SIDAT1 and the buffers. If ENA is not used, the master should wait for 6 VCLK cycles before sending the clock to begin the transaction. This time allows the MibSPI to update the SPIDAT1 register.