Anybody even realize Systick clock source defaults PIOSC/4 (250ns tick)?
Why is there no Tivaware configuration for REG1 {CLK_SRC bit [2]} inside (systick.c)? It seems a reasonable deduction Systick resides inside NVIC, it too clocks PIOSC/4 (4MHz), 250ns tick rate to handle Application interrupt requests from the CPU. The main clock tree Fig 5-5 indicates SYSCLK feeds CPU (Fig 2-1) and no indication NVIC may be using PIOSC/4 (4Mhz) for Systick clock source.
The Systick reload period we often set for the interrupt handler most would assume F=1/p SYSCLK speed is 100x slower then expected. So if you thought Systick reload period you had set for 5ms interrupts it is actually 150ms based on PIOSC &! SYSCLK.
There is no indication Figure 2-1 NVIC even sources SYSCLK, is anyone aware PIOSC/4 may be the default clock source for NVIC too? Why would NVIC not use the same PIOSC/4 clock source as the default imbedded timer Systick?
The fact that Systick concatenated edge times and GPTM edge times mode TnV, TnR registers results are so sporadic perhaps a similar issue? Seemingly NVIC clock source PIOSC/4 interrupt vector handlers swagger due to application speed MSP stacking at SYSCLK speeds. Handler swagger may not be detectable until a very slow GPIO/CCP edge time source challenges NVIC to maintain Synchronous with PLL derived SYSCLK relative to application and CPU instruction decode.
