TMDS570LS31HDK: TMDS570LS31HDK

Hello Karl,

Please check the MDIO clock setting:

The MDIO clock is based on a divide-down of the VCLK3 peripheral bus clock and is specified to run up to 2.5 MHz. Typically 1.0Mhz is used. If the VCLK3 is 80Mhz, the clock divider should be: 80 (79+1)

MDIO_CONTROL = 0x4100004F;

Hi QJ Wang,

Thanks for the reply. The configuration doesn't seem to have any problem with VCLK3 at 80Mhz and the value 0x4104004F is written into the MDIO CONTROL register.

But the registers-view shows 0x410C004F which means fault detect is enabled and there is a PHY fault. The ALIVE and LINK registers both showed 0.

So I guess I have a bad board?

Karl

Hi Karl,

I am not sure if the PHY has problem. Are you able to clear the fault bit by writing 1 to this fault bit? Please try different clock frequency to read PHY ID register, then check if you get a correct return value.

Hi QJ Wang,
There is no change after trying to clear it. I'm not reading the PHY ID, just doing MDIOInit.
This is my modified code

uint32 clkDiv = (mdioInputFreq/mdioOutputFreq) - 1U;
uint32 val = ((clkDiv & MDIO_CONTROL_CLKDIV)
| MDIO_CONTROL_ENABLE
| MDIO_CONTROL_PREAMBLE
| MDIO_CONTROL_FAULTENB);
HWREG(baseAddr + MDIO_CONTROL) = val;

val += 0x00080000;
HWREG(baseAddr + MDIO_CONTROL) = val;

This is the CONTROL register values observed:

initial: 0x810000FF

write: 0x4014004F

read: 0x411c004F

try to clear the fault, write: 0x401C004F

read: 0x411C004F

I tried another board and it exhibits the same behavior.
I checked the clock and found in system.h
#define VCLK3_FREQ 80.000F

Any suggestion?