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TM4C1231H6PZ: Is it possible for the Tiva C to generate a continuous SPI clock and perform transactions on top of it?

Mike Xia
Prodigy 80 points
Part Number: TM4C1231H6PZ

Question from customer:

I have a question regarding the TM4C1231H6PZ that we're thinking of using for our internal-use evaluation board.  (This is to test an internally developed ASIC).

 

The ASIC will have a SPI interface, but because of the way it is designed, the SPI clock also runs some internal logic.  Hence, the SPI clock has to be continuous and stable.

 

Is it possible for the Tiva C to generate a continuous SPI clock and perform transactions on top of it?  It seems all of the timing diagrams on the data sheet indicate gaps in the clock between transactions.  Further, 15.3.4 indicates that "serial clock is held inactive while the SSI is idle".  Would we be able to get around it by continuously feeding the FIFO?

 

If continuous clock is not possible, we would probably need to put some sort of a PLD on the board.

  • 0
    TI__Guru*** 135355 points
    Hello Mike,

    If my understanding of your question is right, then the answer would be that the SPI module will not generate a clock without data to send. In theory you could try and always send 0x00 but that would burden the MCU. Instead, it may be best to not use the SPI clock itself and use a PWM or timer interrupt to generate a clock outside of the SPI module and then bit bang the data when needed. Not the most efficient, but it would not burden the TM4C as much as the alternative. Just some ideas to investigate to maybe avoid the PLD.