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TMS570LC4357: PBIST ignores RINFOL/RINFOU

Ondrej Vaverka
Prodigy 70 points
Part Number: TMS570LC4357


Hello,

could you please provide support? The PBIST is configured to test set of two-port RAMs, but the test fails with result RAMT = 0x101200C which means PBIST_ROM test failed.

When RINFOL/RINFOU registers are checked, their values are 0xFFFFFFFF/0xFFFFFFFF (so default values).

#define MSTGCR_MSTGENA  (0x0Au)
#define MSTGCR_MSTGDIS  (0x05u)

#define MSTGCR_ROM_DIV1  (0u << 8u)
#define MSTGCR_ROM_DIV2  (1u << 8u)
#define MSTGCR_ROM_DIV4  (2u << 8u)
#define MSTGCR_ROM_DIV8  (3u << 8u)

#define PBIST_ALGO_MARCH13_TWO_PORT    (0x04u)
#define PBIST_ALGO_MARCH13_SINGLE_PORT (0x08u)

U32 dbg_pbistResult = 0u;
U32 dbg_RINFOL = 0u;
U32 dbg_RINFOU = 0u;
U32 dbg_pbist_RAMT = 0u;

void pbist_peripherals(void)
{
  U32 ii;

  // Disable PBIST to reset its controller
  systemREG1->MSTGCR = (U32)MSTGCR_MSTGDIS;

  // Enable PBIST controller
  systemREG1->MSINENA = 0x01u;

  // Enable PBIST and set PBIST ROM clock => RTOS_GCLK_MHZ / 4 = 300 / 4 = 75 MHz  (max. 82.5 MHz)
  systemREG1->MSTGCR = (systemREG1->MSTGCR & 0xFFFF0000u) | (U32)MSTGCR_ROM_DIV4 | (U32)MSTGCR_MSTGENA;

  // Wait for at least 64 VCLK cycles in a software loop
  for (ii = 0u; ii < 64u; ii++)
  {
    __asm__ __volatile__ ("nop");
  }

  // Enable PBIST clocks and ROM clock
  pbistREG->PACT = 0x01u;

  // Disable RAM selection override
  pbistREG->OVER = 0x00u;

  // Choose memory testing algorithm
  pbistREG->ALGO = PBIST_ALGO_MARCH13_TWO_PORT;

  // Select RAM group to be tested
  pbistREG->RINFOL = ((U32)PBIST_RINFOL_AWM1    |
                      (U32)PBIST_RINFOL_DCAN1   |
                      (U32)PBIST_RINFOL_DCAN2   |
                      (U32)PBIST_RINFOL_DMA     |
                      (U32)PBIST_RINFOL_HTU1    |
                      (U32)PBIST_RINFOL_MIBSPI1 |
                      (U32)PBIST_RINFOL_MIBSPI2 |
                      (U32)PBIST_RINFOL_MIBSPI3 |
                      (U32)PBIST_RINFOL_N2HET1  |
                      (U32)PBIST_RINFOL_VIM     |
                      (U32)PBIST_RINFOL_RTP     |
                      (U32)PBIST_RINFOL_ATB     |
                      (U32)PBIST_RINFOL_AWM2    |
                      (U32)PBIST_RINFOL_DCAN3   |
                      (U32)PBIST_RINFOL_DCAN4   |
                      (U32)PBIST_RINFOL_HTU2    |
                      (U32)PBIST_RINFOL_MIBSPI4 |
                      (U32)PBIST_RINFOL_MIBSPI5 |
                      (U32)PBIST_RINFOL_N2HET2  |
                      (U32)PBIST_RINFOL_FTU     |
                      (U32)PBIST_RINFOL_CPGMAC_STATE_RXADDR |
                      (U32)PBIST_RINFOL_CPGMAC_STAT_FIFO);

  pbistREG->RINFOU = 0u;

  dbg_RINFOL = pbistREG->RINFOL;
  dbg_RINFOU = pbistREG->RINFOU;

  // Select both Algorithm and RAM information from on-chip PBIST ROM
  pbistREG->ROM = 0x03u;

  // Configure PBIST to run in ROM Mode and launch the PBIST test
  pbistREG->DLR = 0x14u;

  // Wait for result
  while((systemREG1->MSTCGSTAT & 0x01u) == 0u)
  {
    __asm__ __volatile__ ("nop");
  }

  // Check result
  dbg_pbistResult = pbistREG->FSRF0;
  dbg_pbist_RAMT  = pbistREG->RAMT;

  // Disable PBIST clocks and ROM
  pbistREG->PACT = 0x0u;

  // Disable PBIST
  systemREG1->MSTGCR &= ~((U32)0xFu);
  systemREG1->MSTGCR |= 0x5u;
}

Debug variables values after function:

dbg_pbistResult = 1
dbg_RINFOL = 0xFFFFFFFF
dbg_RINFOU = 0xFFFFFFFF
dbg_pbist_RAMT = 0x101200C

Please advice, what could be wrong?

  • 0
    TI__Guru**** 197706 points
    Hello,

    Please wait for PBIST test to complete before checking the status (FSRF0) by polling MSTDONE bit in System Module.

    Can you try only one memory (for example AWM1) to make your code works fine?
  • 0 in reply to QJ Wang
    Prodigy 70 points

    Hello,

    thank you for reply. The code already waits for a PBIST test to complete, see:

      // Wait for result

      while((systemREG1->MSTCGSTAT & 0x01u) == 0u)
      {
        __asm__ __volatile__ ("nop");
      }
      // Check result
      dbg_pbistResult = pbistREG->FSRF0;

    If only one memory is chosen (AWM1), the result is same. It means the registers RINFOL/RINFOU are 0xFFFFFFFF and test fails with RAMT = 0x101200C  (PBIST_ROM test failed...)

  • 0 in reply to Ondrej Vaverka
    TI__Guru**** 197706 points
    Hello,

    Before starting the PBIST sequence, you should ensure that both the instruction cache and data cache are disabled.

    _cacheDisable_() is used to disable the cache.

    What is the value of PBIST_ALGO_MARCH13_TWO_PORT in your code? It should be 0x4 for 2-port using march13n.
  • 0 in reply to QJ Wang
    Prodigy 70 points
    Both caches are already disabled just before PBIST test is launched. The caches are disabled by this assembler code:

    MRC p15, #0, R1, c1, c0, #0 @ Read System Control Register configuration data
    BIC R1, R1, #0x1 <<12 @ instruction cache disable
    BIC R1, R1, #0x1 <<2 @ data cache disable
    DSB
    MCR p15, #0, R1, c1, c0, #0 @ disabled cache RAMs
    ISB

    The value of PBIST_ALGO_MARCH13_TWO_PORT is 0x4. So it is correct. See Example code at the start of this thread.
  • 0 in reply to Ondrej Vaverka
    TI__Guru**** 197706 points
    Thanks Ondrej,

    I will do a test with your code.
  • 0 in reply to QJ Wang
    TI__Guru**** 197706 points

    Thanks Ondrej,

    Please check the revision number of device on your board.

    Because there is one PBIST bug in RevA silicon, please use the workaround if your part is revA. The workaround errata_PBIST_4() is in HL_errata.c.

    Please call this function in HL_sys_startup.c after systemInit()

    Please refer to silicon errata (revA) for the details regarding to this PBIST bug

    http://www.ti.com/lit/er/spnz180d/spnz180d.pdf

  • 0 in reply to QJ Wang
    Prodigy 70 points
    It is revB silicon. So the issue PBIST#4 should be irrelevant.
  • 0 in reply to Ondrej Vaverka
    TI__Guru**** 197706 points
    Hi Ondrej,

    Did you run the single port test for L2RAMW before doing two port test? This test will generate ECC error. I run the two port test, and did not get any error, but I did get the expected data pattern in RAM. I am investigating the PBIST on two port RAM.
  • 0 in reply to QJ Wang
    TI__Guru**** 197706 points
    Hi Ondrej,

    Have you solved the PBIST issue?
  • 0 in reply to QJ Wang
    Prodigy 70 points

    Hello,

    I have finally solved the issue. I am quite sure that problem was in order of instructions.

    This does not work:

      // Disable RAM selection override
  pbistREG->OVER = 0x00u;

  // Choose memory testing algorithm
  pbistREG->ALGO = PBIST_ALGO_MARCH13_TWO_PORT;

  // Select RAM group to be tested
  pbistREG->RINFOL = ...;
  pbistREG->RINFOU = 0u;

    This works fine:

      // Choose memory testing algorithm
  pbistREG->ALGO = PBIST_ALGO_MARCH13_TWO_PORT;

  // Select RAM group to be tested
  pbistREG->RINFOL = ...;
  pbistREG->RINFOU = 0u;

  // Disable RAM selection override
  pbistREG->OVER = 0x00u;

    Also Technical Reference Manual spnu563a is inconsistent in this chapter. Compare Figure 9-2. PBIST Memory Self-Test Flow Diagram with instruction order of the example 9.6.1 Example 1 : Configuration of PBIST Controller to Run Self-Test on DCAN1 RAM (which instruction order does not work for me).

    Could you please confirm this behavior and also confirm this solution as suitable?

  • 0 in reply to Ondrej Vaverka
    TI__Guru**** 197706 points
    Hi Ondrej,

    Thanks. I used the correct order:

    pbistREG->ALGO = algomask;

    /* Select RAM groups */
    pbistREG->RINFOL = raminfoL;

    /* Select all RAM groups */
    pbistREG->RINFOU = raminfoH;

    /* Program OVER = 1h to run PBIST self-test without RAM override. Program OVER = 0 to run PBIST
    self-test with RAM Override.
    */
    /* ROM contents will not override RINFOx settings */
    pbistREG->OVER = 0x0U;

    /* Write a value of 3h to the ROM mask register should the microcode for the Algorithms as well as the
    RAM groups loaded from the on-chip PBIST ROM.
    */
    /* Algorithm code is loaded from ROM */
    pbistREG->ROM = 0x3U;

    /* Start PBIST */
    /* Write DLR (Data Logger register) with 14h to configure the PBIST run in ROM mode and to enable the
    configuration access. This starts the memory self-tests.
    */
    pbistREG->DLR = 0x14U;