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TMS570LC4357: MibSPI Issues

Jordan Zhou
Genius 10080 points
Part Number: TMS570LC4357

Hi, 

One issue about MibSPI.

CPU            : TMS570LC4357

Peripheral Module : MibSPI3

Used Mode      : Multi-Buffer

Design Node     : SPI Master

 

         Many questions as bellow:

1.1   When MOSI transmit 4 word command, is there data received from MISO line and shift into the Rx RAM buffer?

If so, that means there will be offset (4) to get the real data (10 words) by function mibspiGetData?

1.2   For receiving the data from MISO, MOSI need to continue sending out data to keep the clock,

Is it right?

1.3   If all above are right, for this transaction, actual length of send data will be 14 word,

and actual length of receive data will be also 14 word. But offset position where real received data is 4.

Is it right?

         1.4 If all above are right, the DMA will be consider to be used, if the total of Tx length and Rx length more than 128 Words, yes?

         

 

         Using DMA for the transaction of above example, if Command length is 30 words and Receive data 100 words.

         The questions bellow are base the presume theory above.

            Total length is 130 words, for maximize throughput designed the buffer size 65 words, says element size. And frame number is 2.

            The software process is below:

(1)     Compute element size and frame number base on total data length, in this example, e_count = 65, f_count = 2.

(2)     Initial TRANSFER GROUPS.

                 

(3)     Initial Control words in Tx RAM.

        

(4)     Configuaration DMA

        

(5)     Configuration DMA in MibSPI

        

(6)     Start Transaction

(7)     When the total data length change, application will redo the configuration process.

                  Additional Information:

                  

                  

                   My QUESTIONS as below:

2.1   Please help me to check is there some wrong setting in configuration.

2.2   How to evaluate when the transition finish?

The PEND DMA register is used in the logic, the bit of PEND register is corresponding to “nDMA_CHN_**” or “nDMA_REQ_**”?  It is confused to me.

2.3   Found an issue, when total data length changed, and re-configuration finished, the transaction cannot trigger by mibspiTransfer function.

But I tried mibspiInit function, means totally reset initial, followed by the DMA configuration, then the transaction with new e_count and f_count works.

This experiment tell me that the process for DMA configuration to change e_count and f_count is not enough.

I think these is something missed? Could you help me to check?

2.4   Here dmaChannel_t - “nDMA_CHN_**” is the channel in DMACOUNT[channel] or in DMACTRL[channel] ??

Or is there some relation? Could you explain more to me?

2.5   In my understand, there is no need to use DMACTRL [1]、DMACTRL [2]、DMACTRL [3] ……

Could you take an example to explain how to use?

2.6   If the data length in MISO and the data length in MOSI are different, How to configuration DMA?

 

Thanks a lot.

Br, Jordan

  • 0
    TI__Guru**** 197356 points
    Hi Jordan,

    I will study your questions and give you my feedback as soon as I can.
  • 0 in reply to QJ Wang
    TI__Guru**** 197356 points

    Hello Jordan,

    1.1   When MOSI transmit 4 word command, is there data received from MISO line and shift into the Rx RAM buffer?

    QJ> Yes, the received data will shift into RX RAM buffer.

    If so, that means there will be offset (4) to get the real data (10 words) by function mibspiGetData?

    QJ>No, there is no offset. MibSPI slave is triggered by CS signal to TX data.

    1.2   For receiving the data from MISO, MOSI need to continue sending out data to keep the clock,

    Is it right?

    QJ>yes, you are right

    1.3   If all above are right, for this transaction, actual length of send data will be 14 word,

    QJ>If the slave uses the command to decide which data should be txed, so the first 4 words are dummy data, and the following data is the real data.

    and actual length of receive data will be also 14 word. But offset position where real received data is 4.

  • 0 in reply to QJ Wang
    TI__Guru**** 197356 points
    Hi Jordan,

    Your diagram is correct. But master still gets 4-words data during transmitting 4-words data, those received 4-words data are garbage.

    The procedure of the MibSPI+DMA configuration looks correct to me.

    The value in pending register is the DMA channel which is bit-wise. Bit 0 corresponds to channel 0, bit 1 corresponds to channel 1, and so on.
  • 0 in reply to QJ Wang
    TI__Guru**** 197356 points
    How to evaluate when the transition finish?

    QJ> The TGINTFLAG register comprises the transfer group interrupt flags for transfer-completed interrupts (INTFLGRDYx). Bit 16 corresponds to TG0, bit 17 corresponds to TG1, and so on.

    2.3 Found an issue, when total data length changed, and re-configuration finished, the transaction cannot trigger by mibspiTransfer function.

    QJ> You use ONESHOT mode in DMAxCTRL register. After ICOUNTx +1 transfers, the enable bits RXDMAENAx and TXDMAENAx are automatically cleared by the MibSPI, hence no more DMA requests are generated. Your TG0 buffers are also configured as ONESHOT which means:

    A transfer from TGx will be performed only once (one shot) after a valid trigger event at the selected trigger source (you use SW trigger). After the transfer is finished the TGENAx control bit will be cleared and therefore no additional transfer can be triggered before the host enables the TG again

    So you need to set RXDMAENAx and TXDMAENAx, and TGENAx .
  • 0 in reply to QJ Wang
    TI__Guru**** 197356 points
    2.4 Here dmaChannel_t - “nDMA_CHN_**” is the channel in DMACOUNT[channel] or in DMACTRL[channel] ??

    Or is there some relation? Could you explain more to me?

    QJ> They are different. The channel in DMACOUNT[] and DMACTRL[] is the DMA request number or TG number. Each TG can be configured via one dedicated control register, TGxCTRL. There are up to 8 TGs (TG0..TG7). There are 8 DMA request channels corresponding to each TG.


    2.5 In my understand, there is no need to use DMACTRL [1]、DMACTRL [2]、DMACTRL [3] ……

    Could you take an example to explain how to use?

    QJ>Each TG needs one DMAxCTL to configure it's trigger source, trigger event, RX DMA channel, TX DMA channel, and enable/disable. My example code has one function called:
    void mibspiDmaConfig(mibspiBASE_t *mibspi,uint32 channel, uint32 txchannel, uint32 rxchannel)

    2.6 If the data length in MISO and the data length in MOSI are different, How to configuration DMA?
    QJ> One is RX, other is TX. They use different DMA channel, so they have different DMA packet config.
  • 0 in reply to QJ Wang
    Prodigy 110 points
    Hello Wang QJ,


    If so, that means there will be offset (4) to get the real data (10 words) by function mibspiGetData?

    QJ>No, there is no offset. MibSPI slave is triggered by CS signal to TX data.

    David> The offset means the position in RX Buffer RAM, you mentioned that "If the slave uses the command to decide which data should be txed, so the first 4 words are dummy data, and the following data is the real data.", so the first 4 words need ignore.
  • 0 in reply to hongwei ma
    TI__Guru**** 197356 points
    Hi Hongwei,

    Yes, the first 4 words should be ignored in your application.
  • 0 in reply to QJ Wang
    Prodigy 110 points
    Yes, when a different length of buffer RAM length (element size or frame counter) need to transfer, the re-configuration need to execute <please see above (1)-(6)>, this configuration have already include "set RXDMAENAx and TXDMAENAx, and TGENAx" in step (6).
    But it still not work, before these step, i tried to do "mibspiInit", i find it work.
    In my understand, just change element count and frame count, not need to call mibspiInit once more, only to re-initial control register of TX RAM and DMA configuration in enough.
    Could you help me to find the reason?
  • 0 in reply to QJ Wang
    Prodigy 110 points
    Hello Wang QJ:
    Based on this consensus, can i make a conclusion that the data length in TX RAM and in RX RAM in same for each transaction?
    Take the above transaction for example, Send 4 word command for receive 10 word data from slave. Actually, in mibspi RAM, need to 14 buffers TX RAM and 14 buffers RX RAM(first 4 RX RAM should be ignore).
  • 0 in reply to hongwei ma
    TI__Guru**** 197356 points
    Hi Hongwei,

    Yes. The transfer group in slave side is triggered by the CS signal from master side. When master transmits the command, the slave transmits data from its TX RAM too. In your case, it needs 14 buffers. Each buffer contains a 16-bit transmit field, a 16-bit receive field, a 16-bit control field, and a 16-bit status field.
  • 0 in reply to QJ Wang
    Prodigy 110 points
    Hi Wang QJ:

    Thanks for your patiently explain.
    My last issue is:

    Please check my configuration steps for DMA in my first post, the step(1)-step(6).
    when a different length of buffer RAM length (element size or frame counter) will to be transferred, the the step(1)-step(6) will to be executed once again. but i find the transaction not trigger, because RXDMAENAx and TXDMAENAx are still 1, and the DMACOUNT still the initial value, not go to zero.
    Before step(1)-step(6), i tried to do "mibspiInit", i find the transaction work with the new element size or frame counter.

    To be simplify, in other words, the DMA configuration only can work one time after mibspiInit function.

    In my understand, just change element count and frame count, not need to call mibspiInit once more, only to re-initial control register of TX RAM and DMA configuration is enough.

    Could you help me to find the reason?
  • 0 in reply to hongwei ma
    TI__Guru**** 197356 points

    Hi HongWei,

    Enclosed is the main() I used in my test today. It works without any issue. After 1st transfer, please do following config for 2nd transfer (oneshot):

    1. Assigned value to the TGxCTL

    2. enable DMA RX/TX in DMACTL

    3. Define DMA packets

    4. assign DMA channels

    5. enable TG to transmit

    mibspiInit() is not required.

    8475.HL_sys_main.c