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RTOS/TMS570LS3137: Tips on TMS570LS31x

Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Tool/software: TI-RTOS

My customer is developing FW/SW based on FreeRTOS+ TMS570LS31x and got some questions:

1. Our Hercules offer external memory Interfece (EMIF) module to support SDRAM and  Async. RAM. After EMIF initiation, can Hercules directly access external momory instruction set to execute? I.E. Can memory size be expanded through EMIF?

 

2. If 1. is possible, the EMIF module offer 16 bits data bus, do that mean Hercules execute THUMB instruction only?

 

3. If 1 is possible, do sys_link.cmd need to tell compiler to allocate part of the program to external memory?

 

4. If 1 is impossible, can customer used internal flash application program to move partial code to external RAM where EMIF is connected to? Then let CPU to jump to external RAM address to execute the code?

5. Use HALCoGen v04.07.00 verison to generate FreeRTOS as version 8.x, If customer need to upgrade RTOS to newer version, any tips to reduce risk when migrating output of HALCoGen to V10.0.1 that FreeRTOS offered officially?

 

6. As customer can't download Hercules F021 Flash API  library in below link, 

      http://www.ti.com/tool/f021flashapi?keyMatch=F021%20Flash%20API&tisearch=Search-EN-Everything, where can customer get Hercules F021 Flash API v02.01.01 ?

  • Hello,

    1. Our Hercules offer external memory Interfece (EMIF) module to support SDRAM and Async. RAM. After EMIF initiation, can Hercules directly access external momory instruction set to execute? I.E. Can memory size be expanded through EMIF?

    QJ> Yes, the code can be executed in SDRAM. The maximum size for EMIF CS0 is 128MB. Remember that the performance of running code in SDRAM is not as good as running code in internal RAM or flash. The maximum EMIF clock is 50MHz.

    2. If 1. is possible, the EMIF module offer 16 bits data bus, do that mean Hercules execute THUMB instruction only?

    QJ> TMS570LS31x (Cortex-R4) uses ARMv7-R architecture and ARMv7 debug architecture. The ARMv7-R architecture provides 32-bit ARM and 16-bit and 32-bit Thumb instruction sets.

    3. If 1 is possible, do sys_link.cmd need to tell compiler to allocate part of the program to external memory?
    QJ> Yes


    4. If 1 is impossible, can customer used internal flash application program to move partial code to external RAM where EMIF is connected to? Then let CPU to jump to external RAM address to execute the code?
    QJ> yes, you can copy the code and execute the code in SDRAM.

    5. Use HALCoGen v04.07.00 verison to generate FreeRTOS as version 8.x, If customer need to upgrade RTOS to newer version, any tips to reduce risk when migrating output of HALCoGen to V10.0.1 that FreeRTOS offered officially?

    QJ> No, we don't have any tips to port the latest freeRTOS to HALCoGen.


    6. As customer can't download Hercules F021 Flash API library in below link,
    QJ> please use the lower case, there is a bug in the link which doesn't support upper letter case.

    www.ti.com/.../HERCULES-F021FLASHAPI --> www.ti.com/.../hercules-f021flashapi
  • I also have some questions like that have been listed. These response is really helpful.

    But I have some questions based on 3 listed above.

    How to do this using Linker Command File? 

    Does the compiled code will be copied to specific region on SDRAM automatically when CCS entering debug mode?

    Especially in the case SDRAM auto-initialization fails to met power-up constraint, and SDRAM configuration

    procedure must be run in startup code.

  • Hi James

    These reference threads you provided are really resolved my questions.

    Thank you for your response  :)

  • Hello Mason,

    If you don't have any further question, I will close the thread.
  • Hi Wang

    Yeah!

    All helpful response and reference threads are resolved for most of questions.

    The rest of tasks are my practices. and I'm going to new other discussions on E2E if any issues concerned.

    Thanks all for help  : )

    Best Regards,

    Mason