Hi,
I am trying to interface SDRAM using EMIF with example provided with the installation example_emif_sdram.c
/** @example example_emif_sdram.c * This example code configures EMIF module to write and execute from SDRAM * * @b Step @b 1: * * Create a new project. * * Navigate: -> File -> New -> Project * * @image html example_createProject.jpg "Figure: Create a new Project" * * @b Step @b 2: * * Configure driver code generation: * * Navigate: -> TMS570LCxx /RM5x -> Enable Drivers * - Enable EMIF driver * - Enbale GIO driver * - Disable others * * @b Step @b 3: * * Configure pinmux: * - Enable all EMIF pins except EMIF_RNW * - Enable all EMIF outputs including EMIF_CLK * * Navigate PINMUX->Pin Muxing * * Enable checkbox EMIF and disable EMIF_RNW at ball D17 * * @image html emif_pinmux1.jpg "Figure: Pinmux configuration" * * Navigate PINMUX->Special Pin Muxing * * @image html emif_pinmux2.jpg "Figure: Special Pinmux configuration" * * @b Step @b 4: * * Configure EMIF * * Navigate: -> EMIF -> EMIF General * - Enable EMIF SDRAM * - Disable others * * Navigate: -> EMIF -> EMIF SDRAM * - Fill in the timing parameters * * @image html EMIF_config.jpg "Figure: Configuration for ISSI IS42S16400F" * * @b Step @b 5: * * Generate code * * Navigate: -> File -> Generate Code * * @image html generateCode.jpg "Figure: Generate Code" * * @b Step @b 6: * * Modify the linker command file * - Add the follwing under MEMORY * - SDRAM (RWX) : origin=0x80000000 length=0200000000 * - Add the follwing under SECTIONS * - .blinky_section : RUN = SDRAM, LOAD = FLASH0 | FLASH1 LOAD_START(BlinkyLoadStart), LOAD_END(BlinkyLoadEnd), LOAD_SIZE(BlinkySize), RUN_START(BlinkyStartAddr ), RUN_END(BlinkyEndAddr ) * * @image html EMIF_linker.jpg "Figure: Linker command file" * * @b Step @b 7: * * Copy the source code below into your sys_main.c (or) replace sys_main.c with this file. * * The example file example_mibspi_loopback.c can also be found in the examples folder: ../HALCoGen/examples * * @note HALCoGen generates an empty main function in sys_main.c. * */ /* * Copyright (C) 2009-2015 Texas Instruments Incorporated - www.ti.com * * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * */ /* USER CODE BEGIN (0) */ /* USER CODE END */ /* Include Files */ #include "HL_sys_common.h" #include "HL_system.h" /* USER CODE BEGIN (1) */ #include "HL_emif.h" #include "HL_sys_mpu.h" #include "HL_gio.h" #include "HL_het.h" #include "HL_mibspi.h" /* USER CODE END */ /** @fn void main(void) * @brief Application main function * @note This function is empty by default. * * This function is called after startup. * The user can use this function to implement the application. */ /* USER CODE BEGIN (2) */ #pragma SET_CODE_SECTION(".blinky_section") void blinky() { int i; gioSetDirection(hetPORT1, 1); while(1) { gioToggleBit(hetPORT1, 0); for(i=0;i<1000000;i++); } } #pragma SET_CODE_SECTION() extern uint32 BlinkyLoadStart; extern uint32 BlinkyLoadEnd; extern uint32 BlinkySize; extern uint32 BlinkyStartAddr; extern uint32 BlinkyEndAddr; /* USER CODE END */ uint8 emacAddress[6U] = {0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU, 0xFFU}; uint32 emacPhyAddress = 1U; void main(void) { /* USER CODE BEGIN (3) */ int i; uint32 size=(uint32)&BlinkySize; emif_SDRAMInit(); for(i=0;i<size;i++) { ((char *)&BlinkyStartAddr)[i] =((char *)&BlinkyLoadStart)[i]; } blinky(); while(1); /* USER CODE END */ } /* USER CODE BEGIN (4) */ /* USER CODE END */
I used the below configuration
void emif_SDRAM_StartupInit(void)
{
/* USER CODE BEGIN (11) */
/* USER CODE END */
volatile uint32 buffer;
/* Procedure B Step 1: EMIF Clock Frequency is assumed to be configured in the startup */
/* Procedure B Step 2: Program SDTIMR and SDSRETR to satisfy requirements of SDRAM Device */
emifREG->SDTIMR = (uint32)((uint32)4U << 27U)|
(uint32)((uint32)1U << 24U)|
(uint32)((uint32)0U << 23U)|
(uint32)((uint32)1U << 20U)|
(uint32)((uint32)0U << 19U)|
(uint32)((uint32)1U << 16U)|
(uint32)((uint32)3U << 12U)|
(uint32)((uint32)4U << 8U)|
(uint32)((uint32)0U << 7U)|
(uint32)((uint32)1U << 4U)|
(uint32)((uint32)0U << 3U);
emifREG->SDSRETR = (uint32)4U;
/* Procedure B Step 3: Program the RR Field of SDRCR to provide 200us of initialization time */
emifREG->SDRCR = 1605U;
/* Procedure B Step 4: Program SDRCR to Trigger Initialization Sequence */
/** -general clearing of register
* -for NM for setting 16 bit data bus
* -cas latency
* -BIT11_9CLOCK to allow the cl field to be written
* -selecting the banks
* -setting the pagesize
*/
emifREG->SDCR = (uint32)((uint32)0U << 31U)|
(uint32)((uint32)1U << 14U)|
(uint32)((uint32)3U << 9U)|
(uint32)((uint32)1U << 8U)|
(uint32)((uint32)2U << 4U)|
(uint32)((uint32)elements_256);
/* Procedure B Step 5: Read of SDRAM memory location causes processor to wait until SDRAM Initialization completes */
buffer = *PTR;
/* prevents optimization */
buffer = buffer;
/* Procedure B Step 6: Program the RR field to the default Refresh Interval of the SDRAM*/
emifREG->SDRCR = 1098U;
/* Place the EMIF in Self Refresh Mode For Clock Change */
/* Must only write to the upper byte of the SDCR to avoid */
/* a second intiialization sequence */
/* The byte address depends on endian (0x3U in LE, 0x00 in BE32) */
*((unsigned char *)(&emifREG->SDCR) + 0x0U) = 0x80U;
/* USER CODE BEGIN (12) */
/* USER CODE END */
}
Can you please provide the configuration for interfacing SDRAM with EMIF.