Hi,
I have a question about the timing specification in QSSI slave mode.
S10 in Figure 27-32 seems to be outputting data to the master based on the second edge of SSIClk. In this case, it seems that the master device can not receive data properly.
I think that the slave side should output data based on the first edge of SSIClk.
Is my thinking correct?
Best Regards,
H.U