This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

RM48L952: Pinmux File

Part Number: RM48L952
Other Parts Discussed in Thread: HALCOGEN

Can someone confirm for me how to interpret the pinmux.c entries generated by HalCogen below.  E.g. Does this mean ball_K17 is EMIF_nC3, ball_M17 is EMIF_nCS4 and ball_A14 is HET1[26]?

How do registers PINMUX11 and PINMUX12 relate to the PINMMRn? Does PINMUX11 always define the functions for the pins/balls K17, M17, L15, P1 and for only those pins/balls?

pinMuxReg->PINMUX11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_EMIF_DATA_1 | PINMUX_BALL_P1_HET1_24;

pinMuxReg->PINMUX12 = PINMUX_BALL_A14_HET1_26 | PINMUX_BALL_K15_EMIF_DATA_0 | PINMUX_BALL_G19_MIBSPI1NENA | PINMUX_BALL_H18_MIBSPI5NENA; 

  • Hello,
    PINMMR are 32 bit registers. Each byte controls the functionality output on a single terminal.
    For example :
    Ball K17 could be EMIF_nCS[3]/RTP_DATA[14] or N2HET2[9]
    If bit0 of PINMMR11 is set then K17 functionality will be EMIF_nCS[3] - see Table 4-16. Multiplexing and Control of TRM;
    If bit1 of PINMMR11 is set then K17 functionality will be RTP_DATA[14];
    If bit2 of PINMMR11 is set then K17 functionality will be N2HET2[9];
    Table 4-16 shows that PINMMR11 controls K17, M17, L15 and P1 balls functionality.
    Bit 2-0 controls K17 functionality, bit 10-8 controls M17 functionality, bit 18-16 controls L15 functionality and bit 27-24 controls P1 functionality (take a look at section 4.3.1 of device TRM where this is explained).
    So, with:
    pinMuxReg->PINMUX11 = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_L15_EMIF_DATA_1 | PINMUX_BALL_P1_HET1_24;
    You are setting balls K17, M17, L15 and P1 functionality to be as follows:
    K17 - EMIF_nCS[3];
    M17 - EMIF_nCS[4];
    L15 - EMIF_DATA[1];
    P1 - N2HET1[24];

    PINMUX_BALL_K17_EMIF_nCS_3, PINMUX_BALL_M17_EMIF_nCS_4, PINMUX_BALL_L15_EMIF_DATA_1 and PINMUX_BALL_P1_HET1_24 are defined in pinmux.h

    Table 4-16 shows all PINMMR and balls they are controlling.

    Best regards,
    Miro
  • Thanks, especially for explaining how PINMUXn relates to the PINMMRn.