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TM4C1290NCPDT: EEPROM vs. Flash

MattLin
Intellectual 1050 points
Part Number: TM4C1290NCPDT

Hi Team,

My customer is using the TM4C1290NCPDT and needs about ~3-4 kbytes of general data storage. These are separated into ~10 blocks with 300-400 bytes each and will be rewritten ~5k times over the lifetime of the product. They had a few questions in regards to EEPROM vs. Flash write characteristics in regards to the TM4C1290NCPDT.

For EEPROM, how would you design the system to avoid situations where a "copy to the copy buffer is required, the copy buffer requires an erase" since they have unacceptable maximum write times.  Could you provide a little more insight into how this works?  Once the 8th write is invoked, does this always require an erase?  Does this counter reset after a power cycle?

For Flash, the main concern is in the datasheet where it states, "When a Flash memory operation write, page erase, or mass erase is executed in a Flash bank, access to that particular bank pair is inhibited." The application already takes >300k of read-only memory and they want to avoid stalling the regular periodic process of the application.

It seems like we're already using some portion of all 4 banks of flash to store the application.  Other than move instructions into SRAM to keep the application going, are there any other alternatives to slice out a small (3k - 4k) piece of flash memory that wouldn't affect execution of the application?

Lastly, there is a nice description of what a sector of flash is, but they're confused as to what constitutes a page of flash as described in the timing characteristics.

Can you please clarify their questions as well as advise on how you think to best approach their issue with either EEPROM or Flash?

Thanks,

Matt

  • 0
    TI__Guru 72500 points
    With 3 to 4KB of data reprogrammed ~5K times there is no way to avoid the erase time. What is their maximum write time? If they cannot accept 60mS to write 16 32-bit words (64 bytes), or 240mS to write 400 bytes they need to look for some other form of off-chip non-volatile memory. If they can, then use the emulated EEPROM. Using the main flash bank is not practical.
  • 0 in reply to Bob Crosby
    TI__Intellectual 1050 points

    You mentioned that the 60 ms write time is for 16 32-bit words (64 bytes).  I was under the impression that this was only for 1 32-bit word (4 bytes) from Table 27-33 EEPROM Characteristics. Can you please confirm this is correct?

    Additionally, given that we're looking at the potential of only writing 5k times to any given memory location over the life of the product, can we safely assume that we'll always be in the "<10% of EEPROM endurance used" category?  If not, I see that the max write times could scale up to nearly 1800 ms.  Out of curiosity, does this tend to scale linearly?

  • 0 in reply to MattLin
    TI__Guru 72500 points
    The 60mS time is for the case when the page is full and needs to be moved to the copy buffer and the copy buffer is full. Therefore two erases are required. This can happen when a single 32-bit word in the block is updated, but it only happens once even when all 16 words in the block are updated. (In other words, the worst case time is roughly the same whether you update one word or 16.)

    Yes, 5K cycles means they are definitely always within the first 10% of the endurance. The time does not scale linearly. It stays mostly constant and then increases exponentially near the end of life as traps form in the erase oxide and increase the erase time.