TM4C1294NCPDT: EPI HB16: Wrong statement of IRDYDLY in datasheet?

Livio Brunner

Part Number: TM4C1294NCPDT

Hi Everyone

I use the TM4C1294NCPDT und try to connect an FPGA with the EPI in HB16 Mode.
With the iRDY signal I would like to stall the access for read and for write operations.

In the Datasheet figure 11-5 on page 836 it is shown what happens if iRDY is asserted, depending on the IRDYDLY configuration.
The Register "EPIHB16TIME" on Page 931 under IRDYDLY confirms the figure 11-5.

Depending on the IRDYDLY configuration, the access BEGINNS to stall 1,2 or 3 EPI clockcycles after iRDY goes LOW.
After the stalling time (in figure 11-5 its only 1 EPI clock) the datatransfer continues.

My measurements shows, that independent of the IRDYDLY configuration, the access always beginns to stall after 3 EPI clockcycles.
BUT depending on the IRDYDLY configuration the time after iRDY goes HIGH again is different.
For IRDYDLY=1 its 1 EPI clock after iRDY is HIGH again. For IRDYDLY=3 its 3 EPI clock after iRDY is HIGH again.

My attached Figures:
1: IRDYDLY = 1: it takes 3 EPI cc to stall.
2: IRDYDLY = 1: carries on 1 EPI cc after iRDY is HIGH again.
3: IRDYDLY = 3: it takes 3 EPI cc to stall.
4: IRDYDLY = 3: carries on 3 EPI cc after iRDY is HIGH again.

With my understanding and this measurements the concept of the IRDYDLY is wrong in the figure 11-5 on page 836 as well as Page 931.
IRDYDLY does not influence the start of the stalling but how long it takes to recover from the stall.

I am very thankful if you have some more information about the IRDYDLY or could prove my findings as wrong.
Kind regards Livio