Hi,
We use the described TMS570 uC to develop a mobile machine device which shall reach the SIL2 Safety level.The datasheet describes a maximal system clock of 180MHz (HCLK). We want to setup the internal PLL to use this maximum frequency. The question is, if we will use an external crystal oscillator with its own tolerance, how can we ensure that the real configured system clock is not over 180MHz?
Example:
Crystal frequency: 16 MHz (With tolerance max 16.001MHz)
Theoretic case: 16MHz -> PLL -> 180MHz
Worst case: 16.1MHz -> PLL -> 180.01125MHz
So the worst case is out of the specified datasheet range. For our application it is important to use the maximal possible system clock. How the maximal system clock can be used in this case? Are there any further TMS570 documentations which describes additional tolerances of the clock to solve this safety issue?
I am sure that there will be no problems with the TMS570 in this case, but we need to prove that.
Best regards,
Juri
