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Original question:

HALCoGen 04.04.00 MibSPI bug with TMS570LS2124

CCS/TMS570LC4357: Mibspi CS pin can not deactivate

hongwei ma
Prodigy 110 points

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Tool/software: Code Composer Studio

Hi :

I have a question:

By set CSHOLD = 1 in last buffer, the CS pin can be hold active,

but after transmit finish, how to go to set the CS pin go to deactivate status?     

  • 0
    TI__Mastermind 21425 points

    Hello,

    CSHOLD Bit has different meanings for Master and Slave mode.  In Master mode, if the CSHOLD bit is set in the control field of a word, the chip select signal will not be deactivated until the next control field is loaded with new chip select information. For Slave mode in Multi-buffered mode, if the CSHOLD bit in a buffer is set to 1, then the MibSPI does not wait for the SPICS pins to be deactivated at the end of the shift operation to copy the received data to the receive RAM. With this feature, it is possible for a slave in multi-buffer mode to do multiple data transfers without requiring the SPICS pins to be deasserted between two buffer transfers. When the slave is in Compatibility mode, the slave does not require the SPICS pin to be deasserted between two buffer transfers. The CSHOLD bit of the slave will be ignored in compatibility mode. This is described in Section 28.2.6.5.2 of device TRM ( )

    Which version of HALCoGen are you using? In the las version of HALCoGen there is two check boxes for Chip Select Hold.

    One is for holding CS active after transmission of each buffer and the other is to hold CS active after transmission of last buffer.

    Best regards,

    Miro

  • 0 in reply to Miro
    Prodigy 110 points

    Hello:

    I used in master mode. and i did not use the HALCoGen tool, i directly use register.

    The background of this question is bellow:

       

    Configure TG0 (size is 65 word), there is one transaction need 130 word, so need TG0 transmit two times. 

    but i found CS goto deactivate after first TG0, So the also configure CSHOLD in last tx buffer control. 

     pMibspiRam->tx[e_count-1].control |= (uint16)((uint16)1 << 12U);

    By this way, CS not goto deactivate, but after totally finish, CS can not goto deactivate, this is wrong.

    Could you help me how to make CS deactivate? 

  • 0 in reply to hongwei ma
    TI__Mastermind 21425 points

    Hello,

    Try with clearing CSHOLD bit after your last transaction.

    Best regards,

    MIro

  • 0 in reply to Miro
    Prodigy 110 points
    Hello:

    I try to cleared CSHOLD bit of the last buffer of TG, but not work, the CS still active.
  • 0 in reply to hongwei ma
    TI__Mastermind 21425 points
    Hello,
    Do you have progress with this issue?

    Best regards,
    Miro
  • 0 in reply to Miro
    Prodigy 110 points
    Hello,
    Still not resolve this problem.
    I tried use "SPI Pin Control Register" to make CS pin deactivate.
    It is useful BUT there is side effect, next round of SPI communication can not start up .
    So i have to initial SPI module every time before SPI communication, it is high cost.
  • 0 in reply to hongwei ma
    Prodigy 110 points
    Hello Mr Miroslav:
    Could you help me to fix this issue?
    Look forward your reply.
  • 0 in reply to hongwei ma
    TI__Guru**** 199346 points
    Hi HongWei,

    The bit 12 of the control field of the last TXRAM buffer is cleared in your MibSPI configuration. This is why the CS is de-asserted after transferring 65 words (number of buffers in your transfer group).
  • 0 in reply to QJ Wang
    Prodigy 110 points
    Hi QJ:

    I set the CSHOLD bit in last buffer on purpose to keep CS pin low level between transfer groups, because they are composed one whole transaction.
    And after transfer finish, i tried to cleared CSHOLD bit of the last buffer, but failed, the CS pin still keep low level, can not goto high level.
  • 0 in reply to hongwei ma
    TI__Guru**** 199346 points
    Hi Hongwei,

    After DMA transferred the whole block of data, the TG is disabled and DMX TX/RC are also disabled. For next transfer, you need to reconfigure the TX RAM (control and data), the CS should de-asserted.