TMS570LC4357: EMIF nDQM configuration

Hi team

My customer is using TMS570LC4357. They want to communicate FPGA with EMIF.

The following is the code

 emifREG->CE3CFG = (0U  << EMIF_BIT_SS)       |
                    (0U  << EMIF_BIT_EW)       |
                    (1U  << EMIF_BIT_W_SETUP)  |  
                    (14U << EMIF_BIT_W_STROBE) |  
                    (0U  << EMIF_BIT_W_HOLD)   |
                    (15U << EMIF_BIT_R_SETUP)  |  
                    (15U << EMIF_BIT_R_STROBE) |  
                    (0U  << EMIF_BIT_R_HOLD)   |
                    (1U  << EMIF_BIT_TA)       |
                    (1U  << EMIF_BIT_ASIZE);     

But they found that the timing of the nDQM signal observed through the FPGA is not normal. 

What is the normal timing of the nDQM signal of the TMS570LC4357? Is there a register to configure it?

BR,

Susan