TMS570 reset when enabling RTI

Hi,

When we configure the RTI of the TMS570, a reset occurs.

The initialisation procedure is provided herafter.

Could you help us to find what kind of mistake we have done?

Regards

Benoit

procedure MARTM_INI_RTI_INIT (pU32_RTI_FREQ_MHZ                          : in TUINT32;
                                 pU32_INIT_STATE_DURATION_US                : in TUINT32) is
      LU32_COMPARE0 : TUINT32;

      -- RTICOMP0
-- UndCC_Begin(All-CallResult), Ignore for this context.
-- UndCC_Begin(All-IdentifierNoOverload)
      LS_RTICOMP0 : TS_RTICOMP0;
      for LS_RTICOMP0'Address use To_Address(K_RTI_BASE_ADDR + 16#50#);

    -- RTITBCTRL
      LS_RTITBCTRL : TS_RTITBCTRL;
      for LS_RTITBCTRL'Address use To_Address(K_RTI_BASE_ADDR + 16#04#);

      -- RTICPUC0
      LS_RTICPUC0 : TS_RTICPUC0;
      for LS_RTICPUC0'Address use To_Address(K_RTI_BASE_ADDR + 16#18#);

      -- RTISETINTENA
      LS_RTISETINTENA: TS_RTISETINTENA;
      for LS_RTISETINTENA'Address use To_Address(K_RTI_BASE_ADDR + 16#80#);

      -- RTIGCTRL
      LS_RTIGCTRL : TS_RTIGCTRL;
      for LS_RTIGCTRL'Address use To_Address(K_RTI_BASE_ADDR + 16#00#);

      -- RTIINTFLAG
      LS_RTIINTFLAG : TS_RTIINTFLAG;
      for LS_RTIINTFLAG'Address use To_Address(K_RTI_BASE_ADDR + 16#88#);
-- UndCC_End(All-CallResult), Ignore for this context.
-- UndCC_End(All-IdentifierNoOverload)

   begin

      ------------------------------------------------------------------------------
      --                         *** RTI Timebase Control ***
      ------------------------------------------------------------------------------
      -- Free running Counter 0 (RTIFRC0) clocked by the internal up counter 0 (RTIUC0)

      LS_RTITBCTRL.TBEXT  := 16#0#;
      ------------------------------------------------------------------------------
      --                         *** RTI Compare Up Counter 0 ***
      -- The compare up counter 0 register holds the value to be compared with prescale counter 0 (RTIUC0).
      -- When the compare shows a match, the free running counter 0 (RTIFRC0) is incremented
      ------------------------------------------------------------------------------
      LS_RTICPUC0.CPUC0     := K_COUNTER_BLOCK_0_PRESCALER - 1;

      -- Write the RTI Compare 0 (RTICOMP0) value to generate an interrupt after TIME_INIT
      LU32_COMPARE0 := pU32_RTI_FREQ_MHZ*pU32_INIT_STATE_DURATION_US;
-- UndCC_NextLine(All-Division). Division by zero impossible here.
      LU32_COMPARE0 := LU32_COMPARE0/(K_COUNTER_BLOCK_0_PRESCALER);
      LS_RTICOMP0.COMP0 := LU32_COMPARE0;

      ------------------------------------------------------------------------------
      --                         *** RTI Global Control ***
      ------------------------------------------------------------------------------
      LS_RTIGCTRL.CNT0EN   := 16#1#;  -- Counter 0 enabled

      -- Clear INT0-2 flags
      LS_RTIINTFLAG.INT0 := 16#1#;
      LS_RTIINTFLAG.INT1 := 16#1#;
      LS_RTIINTFLAG.INT2 := 16#1#;

      ------------------------------------------------------------------------------
      --                         *** RTI Set Interrupt Enable ***
      ------------------------------------------------------------------------------
      LS_RTISETINTENA.SETINT0 := 16#1#;  -- Enables Compare Interrupt 0
      LS_RTISETINTENA.SETINT1 := 16#1#;  -- Enables Compare Interrupt 1
      LS_RTISETINTENA.SETINT2 := 16#1#;  -- Enables Compare Interrupt 2

      -- Enable interrupts for channels 2, 3, 4 and 9 (RTI Compare0, RTI Compare1, RTI Compare2 and GIO high-level)
      LS_REQENASET0.REQENASET0 := 16#21C#;

   end MARTM_INI_RTI_INIT;

end MARTM_INI_RTI_INIT_PK;