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TMS570LS0714: Could not use MibSPI3 chip select 5 on TMS570LS0714 with PZ (100 pins) package

Benoit Tarrade
Prodigy 30 points
Part Number: TMS570LS0714
Other Parts Discussed in Thread: HALCOGEN

Hi,

As part of our product development process, I am using spi communication to transfer data between sensor boards and the main board. In this context,  I successfully used MibSPI 1 and 3, thanks to HALCogen's generated driver on MibSPI1 chip selects 0 & 1 , and Mibspi3 chip select 0 as well.

However, I could not have the 5th chip select of Mibspi 3 to behave as the other ones.

The only thing to be modified, between chip select 0 and chip select 5, to my understanding, is the CSNR field of TxRam buffer of one mibspi, using proper pinmuxing (MibSpi3NCS5 on pin 37, with mibspi3 driver enabled),

Configuration recap :

Mibspi3 driver enabled

pin 37 pinmuxed as MibSpi3 NCS5

Using SPI_CS_5 in code to target NCS5 ( 0xDFU according to Halcogen)

Note : I was able to correctly toggle this pin (37) using its pinmuxed het1_31 counterpart configured as a GPIO, and successfully transmit/data over SPI bus.

Note 2 : I am using a custom driver wrapper to reconfigure transfer groups on-the-fly, depending on the data length (> 128) . This driver has full control over TXRam buffer content, including CSNR and CSHOLD fields which are required to toggle the right CS line.

I looked several times into the chip's datasheet and the user guide and could not find any clue about what I am doing wrong.

Any idea ?

Many thanks,

Benoit

  • 0
    TI__Guru**** 196776 points
    Hello Benoit,

    Please check the pinmmr[9] manually to make sure the MibSPI3nCS[5] bit (bit 9) is set, and other bits (9, 10, 11) are cleared.
  • 0 in reply to QJ Wang
    Prodigy 30 points

    Hello Mr.Wang,

    Thank you for your reply.

    I've checked in PINMMR9 pinMuxReg register, as defined by HALCOgen's code, and the 9th bit is correctly set. There is no obvious conflicts between this pin pinmuxing.

    I double checked with the datasheet, but found nothing relevant by now.

    I had one thought however, do the Chip select pin and regular gios differ from a power point of view? I mean, gios could be configured as push-pull output with lets say 10 mA of current sourcing/sinking. Does the chip select pin use a different hardware topology?

    We have a 3.3V/10kOhms pullup on the chip select line of the spi boards ; nonetheless other boards with the exact same configuration work just fine with regular chip selects from MibSpi1.

    Thank you for your time,

    Best regards,

    Benoit

  • 0 in reply to Benoit Tarrade
    TI__Guru**** 196776 points

    Hi Benoit,

    The pull-up should be fine. Please configure the pin (37) to MibSPI3nCS[5] under pinmux. 

    1. Configure nCS[5] as GIO Output (SPI Pin Control Register 0/1 (SPIPC0/1)),

    2. then toggle this pin using SPI Pin Control Register 3

    3. probe pin 31.

    This will show if nCS[5] is routed to pin 31 correctly.I am sorry I don't have HW to test LS0713 PZ package at this moment.

  • 0 in reply to QJ Wang
    Prodigy 30 points

    Hi Mr.Wang,

    Thank you for your advices, gio behaves as expected.

    I did some more tests and found that I had to manually configure MIBSPI3 NCS5 pin as a SPI function pin
    After the device has booted, this pin is defaulted to a gio, as stated in the datasheet, hence it needs to be reconfigured manually.
    I am also pointing out that HALCOgen tool does not provide ways to configure the behavior of this particular pin (ports functions are only available for NCS0 for this package).

    Hence, here is what I did :

        /* Unlock Pin Muxing */
    kickerReg->KICKER0 = 0x83E70B13U;
    kickerReg->KICKER1 = 0x95A4F1E0U;

    /* Clean pinmuxing on pin 37 and reroute mibspi3 ncs5 on pin 37 */
    pinMuxReg->PINMMR9 = (pinMuxReg->PINMMR9 & ~(0b1111 << 8U)) | (1U << 9U) ;
    mibspiREG3->GCR1 |= (uint32_t) (1U << 1U);  /* Enable mibspi3 as spi master */
    mibspiREG3->PC0  |= (uint32_t) (1U << 5U);  /* Configure MIBSPI3 NCS5 as spi pin */
    mibspiREG3->PC1  |= (uint32_t) (1U << 5U);  /* Configure MIBSPI3 NCS5 as output*/

    /* Relock Pin Muxing */
    kickerReg->KICKER0 = 0x0U;
    kickerReg->KICKER1 = 0x0U;

    All those steps might not be necessary, as pinmuxing shall be covered by Halcogen's pinmux code, but it helps to manually write into pinmux registers on a debug session.
    I guess configuring NS5 as an output is redundant as well and not necessary as its function is governed by spi peripheral, not by gio.

    Many thanks for your help,

    Benoit