TMS570LS0714: TMS570LS ,There are two CPUs inside the chip, which need to check the code?

Hello Zhao,

TMS570LS uses ARM cortex-R4F CPU. The ARM cortex-R4F CPU is implemented with a checker cortex-R4F CPU in a lock-step configuration. Both the application CPU and the diagnostic CPU are fed the same input signals, which results in both CPUs running the same software. The diagnostic and application CPUs should generate the same output. The core compare module (CCM) compares the CPU outputs and flags all mis-compares to the ESM.The lockstep diagnostic is continually operating from power-on reset.

The CCM logic provides self test and error forcing capability via software triggered hardware. The self test ensures that the CCM compare logic is working properly. The error forcing capability allows you to test the system level response to a lockstep miscompare.

The HALCoGen generates example code (selftest.c) showing you how to enable the selftest, fault injection, etc. You don't need any verification code to verify the comparison.

HI Zhao,

1. The dual core lockstep detects failures at the core boundary on a cycle by cycle basis. Any difference in the core compare bus outputs of the CPUs is flagged as an error. The device is in lockstep mode after reset and start comparison automatically, so you don't need to enable and start.

2. CPU selftest (STC):   This is used to test the lockstep CPUs at a transistor level. This test must be triggered by the software. It is suggested to run this test during startup. When test execution is complete, the CPU will be reset. You don't need a loop to run the self test.

3. CCM-R4F: The CCM logic provides self test and error forcing capability via software triggered hardware. The self test ensures that the CCM compare logic is working properly. The error forcing capability allows you to test the system level response to a lockstep miscompare. You don't need a for loop to call this selftest.

Please refer to the halcogen generated sys_startup file and APIs in selftest.c file.

Hello whong,

I am sorry for my confused message. You can do the self test whenever you need based on your application.   

STC generates a CPU reset after completion of the test regardless of pass or fail. You can run the STC test during startup or can divide STC into 24 or fewer intervals and run them during normal operation. If STC is ran only on startup, your software need not save the CPU contents since the reset caused will go through all startup configurations.This is why I suggest you to run this test at boot time. If your system keeps running for long time (for example 12 hours) without any reset (nRST, poweron reset), you may need to do more STC selftest. Please refer to chapter of TRM: spnu507.pdf

PSCON: power state controller -- chapter 3 of TRM spnu507.pdf

Efuse: Electrically programmable fuses are used to configure the device after deassertion of PORRST. Please refer to chapter 29

Flash: Please refer to sector 5.7 for flash Diagnostic Modes

Hello whong,

Is there a plan to get the safety certification for your product? What ASIL or SIL level is required?

It 's better to ask the assessor about if you need more CPU selftest?

Hello Whong,

Please refer to our functional safety manual. If your system needs SIL4, you probably need all the self tests. Please check with the assessor for your product.