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TMS570LS3137: Lock step exception handler

sreenivasan m
Genius 3705 points

Part Number: TMS570LS3137

Hi Team,

For lock step exception handler, could see that we need to clear channel 31 group1 and channel 2 in group2.
Let me know if we need to handle further on this. Also, can you provide details on shadow status register details.

  • 0
    TI__Guru**** 200206 points

    Hello,

    In lock step mode, a CPU compare error asserts “CCM-R4F - compare” and “CCM-R4F self-test error” flags to the ESM. So both of them should be cleared.

    To avoid an erroneous CCMR4F compare error, the application software needs to ensure that the CPU registers of both CPUs are initialized with the same values before the registers are used.

    ESMSR2 is cleared after nRST. The shadow register (ESMSSR2) maintains the error flags until power-on reset (PORRST) is asserted. Because nRST clears the flags in ESM status register 2 (ESMSR2), the user has to read the shadow register to debug the failures after RST pin goes back to high.

  • 0 in reply to QJ Wang
    Genius 3705 points

    Hi Wang,

    Can you please provide more details on Shadow registers? Could not see details in spnu499c.pdf.

  • 0 in reply to sreenivasan m
    Genius 3705 points

    Also, CCM-R4F self-test error happens only during self test and not during normal execution.

  • 0 in reply to sreenivasan m
    TI__Guru**** 200206 points

    Hello,

    1. ESMSSR2 is the shadow register. This register can maintain the error flags of group2 after nRST. The value of ESMSSR2 is only affected by nPORRST.

    2.  In lock-step mode, the inputs to the CCM compare logic are from CPI1 and CPU0, the difference in the output bus of compare logic may be caused by either 2 inputs or by the compare logic. This is why both “CCM-R4F self-test error” and “CCM-R4F -compare” are set. 

  • 0 in reply to QJ Wang
    Genius 3705 points

    Hi Wang,

    Can you please provide details of shadow register bit fields and where can we find it in technical reference manual.

  • 0 in reply to sreenivasan m
    TI__Guru**** 200206 points

    Hello,

    12.4.16 ESM Status Shadow Register 2 (ESMSSR2)

    bot 0: channel 0 of Group 2

    bit 1: channel 1 of Group 2

    ...