Hello there,
With the MCU TMS570LS3137PGE package, I would like to know how many TGs the 128-location TXRAM can be divided into. In para. 25.1.2.1 of the TRM, it is saying that:
Number of buffers for each peripheral (or data source/destination, up to 128 buffers supported) or group (up to 8 groupings)
In para. 25.9.34 TGx Control Registers (TGxCTRL) of the same TRM spnu499c, it refers the reader to the device datasheet.
Each TG can be configured via one dedicated control register. The register description shows one control register (x) that is identical for all TGs. For example, the control register for TG2 is named TG2CTRL and is located at base address + 98h + 4 × 2. The actual number of available control registers varies by device.
However, I cannot find this info in the spns162c datasheet.
With the IAR EWARM debugger, I see that there are TG0CTRL through TG15CTRL. Does this mean that there are 16 TGs? If so is it in contradiction with the first statement above?
Thank you for clarifications.
Regards.
