Hello there,
In the TRM spnu499c para. 15.2.2 for VIM, there is a mention "When an IRQ interrupt is received, the CPU disables other IRQ interrupts by setting CPSR bit 7. When an FIQ interrupt is received, the CPU disables both IRQ and FIQ interrupts by setting CPSR bits 6 and 7."
Fine with the FIQ as it will preempt the ISR under service. But how about making one particular long ISR preemptable by other higher priority IRQs?
I'm using the mode "Hardware vectored interrupts (automatically dispatch to ISR, IRQ only)" at para. 15.2.3.
Thank you!
