Other Parts Discussed in Thread: HALCOGEN,
Hello,
We are using TMS570LS3137 controller and used HACOGEN tool to generate the code. i have few doubts related to pbist self test code generated by HALCOGEN:
Function name : afterSTC()
Testing Dual port memories using PBIST.
Why is RAM ECC and FLASH ECC tests are between PBIST dual port test ?
Below is the code snippet referred in this case:
pbistRun( (uint32)0x00000000U /* EMAC RAM */
| (uint32)0x00000000U /* USB RAM */
| (uint32)0x00000000U /* DMA RAM */
| (uint32)0x00000200U /* VIM RAM */
| (uint32)0x00000040U /* MIBSPI1 RAM */
| (uint32)0x00000000U /* MIBSPI3 RAM */
| (uint32)0x00000000U /* MIBSPI5 RAM */
| (uint32)0x00000000U /* CAN1 RAM */
| (uint32)0x00000000U /* CAN2 RAM */
| (uint32)0x00000000U /* CAN3 RAM */
| (uint32)0x00000000U /* ADC1 RAM */
| (uint32)0x00000000U /* ADC2 RAM */
| (uint32)0x00001000U /* HET1 RAM */
| (uint32)0x00000000U /* HET2 RAM */
| (uint32)0x00000000U /* HTU1 RAM */
| (uint32)0x00000000U /* HTU2 RAM */
| (uint32)0x00000000U /* RTP RAM */
| (uint32)0x00000000U /* FRAY RAM */
,(uint32) PBIST_March13N_DP);
/* Test the CPU ECC mechanism for RAM accesses.
* The checkBxRAMECC functions cause deliberate single-bit and double-bit errors in TCRAM accesses
* by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error
* in the ECC causes a data abort exception. The data abort handler is written to look for
* deliberately caused exception and to return the code execution to the instruction
* following the one that caused the abort.
*/
checkRAMECC();
/* Test the CPU ECC mechanism for Flash accesses.
* The checkFlashECC function uses the flash interface module's diagnostic mode 7
* to create single-bit and double-bit errors in CPU accesses to the flash. A double-bit
* error on reading from flash causes a data abort exception.
* The data abort handler is written to look for deliberately caused exception and
* to return the code execution to the instruction following the one that was aborted.
*
*/
checkFlashECC();
flashWREG->FDIAGCTRL = 0x000A0007U; /* disable flash diagnostic mode */
/* Wait for PBIST for CPU RAM to be completed */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while(pbistIsTestCompleted() != TRUE)
{
}/* Wait */
/* Check if CPU RAM passed the self-test */
if( pbistIsTestPassed() != TRUE)
{
/* CPU RAM failed the self-test.
* Need custom handler to check the memory failure
* and to take the appropriate next step.
*/
pbistFail();
}
/* Disable PBIST clocks and disable memory self-test mode */
pbistStop();
Thanks,
Kalyan
