• State Resolved
  • Locked Locked
  • Replies 6 replies
  • Subscribers 30 subscribers
  • Views 669 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TM4C1294KCPDT: Unused VBat pin

Genatco
Guru 55913 points
Part Number: TM4C1294KCPDT

Does errata ELEC#02 relate to unused VBAT preferred practice for unused pins (Table 26-7) VBAT tied to VDD? Should VBAT pin 68 "May be damaged" leads to any other pins being effected such as VDD being pulled down to GND when VBAT has been tied to VDD?

It seems ELEC#02 lists no specific conditions of pin 68 use as previous clarified in datasheet that otherwise seems to contradict Table 26-7.  Does an errata hive a higher priority than tables previously defined unused pins practice in the datasheet? If true why has the datasheet Table 26-7 not been corrected to reflect ELEC#02 if such an errata can directly effect VDD? Perhaps pin 68 preferred practice should not be tied to VDD and instead included a series resistor to stop issues from an unused VBAT pin.

  • 0
    TI__Guru 72500 points

    The errata document takes precedence as it is more recent. If the ramp rate of Vdd exceeds 0.7V/uS then leaving the unused VBAT pin not connected(NC) would be the preferred practice. Connecting to Vdd with an RC circuit to control the slew rate would be an acceptable practice.

  • 0 in reply to Bob Crosby
    Guru 55913 points

    Hi Bob,

    Since the errata is know to exist and as you seem to infer also effects unused pins table 26-7 should have been updated in later revision datasheets as not to confuse the issue when Hibernate module is not being used. Otherwise errata precedence of ELEC#02 was later determined should be a bit more specific as to the severity or impact to VBAT pin as it relates to previously declared unused pins in table 26-7. The conclusion can be drawn when the hibernate module is not being used per table 26-7 VBAT and ELEC#02 is not a concern. 

    Our custom PCB +5v ramp up rate and enable pin produces a soft start into 3v3 LDO, should avoid damaging VBAT. Another concern is for others in the forum who have reported MCU short issue may have tied VBAT to VDD. Seemingly table 26-7 then incorrectly specifies being a preferred practice even when Hibernate module is not being used.

    Note: TM4C design guide seems to concur with Table26-7

    "If a dedicated battery is not going to be used, VBAT can be connected to the same net driving the VDD pins without adding the RC filter."

  • 0 in reply to Bob Crosby
    Guru 55913 points

    Hi Bob,

    Accordingly the errata ELEC#02 should be better clarified as to conditions of concern other than VBAT ramping time. Likewise if the Hibernate module input XOSC0 is tied to ground and hibernate peripheral is not enabled in software, how can VBAT pin ever be an errata concern?

    ELEC#02 was known to exist in RA1 silicon, why was it not fixed in later revisions if the impact is so severe as to actually damage the pin and contradict table 26-7?

    Seemingly ELEC#02 is not as severe under un-used pin conditions or it would have been corrected in later silicon revisions!

  • 0 in reply to Genatco
    TI__Guru 72500 points

    Hi BP101,

    Advisory ELEC#02 is because the ESD protection circuit on the VBAT pin is designed to trigger an SCR to help protect the pin from damage in an ESD event. It triggers on the very fast rise time of the voltage during an ESD event. If the supply voltage rises too quickly, it can inadvertently turn on the SCR. A supply voltage, unlike an ESD event is a long time event and therefore has enough energy to cause damage to the device. The advisory is therefore independent of whether the Hibernate module is used or not. Most designs,like yours, the rise time of the supply voltage is slow enough that this issue is not of concern.

  • 0 in reply to Bob Crosby
    Guru 55913 points

    Hi Bob,

    Bob Crosby said:
    VBAT pin is designed to trigger an SCR to help protect the pin from damage in an ESD event

    Seemingly not a very good method to stop ESD if it can be easily shorted. Perhaps it should be omitted and updated in RA3 silicon with typical 3v3 ESD device..

  • 0 in reply to Genatco
    Guru 55913 points

    One other concern would be rapid brown out where VBAT suddenly dips to +1.4v then rapidly rises <0.7v/µS up to 3v3. Brown out condition seemingly may not produce the same slower ramp period as soft start ramp up of typical buck regulators.