Part Number: TMS570LS1224
Tool/software: Code Composer Studio
Hi there
I want to send and receive data with mibspi interface. the tms570 acts as slave. there are 2 us time between two consequtive transaction. the cpu is working with a 160 MHz clock. so the there is 320 cycles between two transaction.as much as I know the interrupt latency on cortex R CPUs are very low (less than 20 cycles). but when I write some code in mibspi I lose some interrupts. I don't think my code takes more than 10 cycle. this is my ISR. I have set the length of buffer of transfer group to 1.
void mibspiGroupNotification(mibspiBASE_t *mibspi, uint32 group)
{
/* enter user code between the USER CODE BEGIN and USER CODE END. */
/* USER CODE BEGIN (27) */
mibspiRAM3->tx[0].data = LUT[mibspiRAM3->rx[0].data];
/* USER CODE END */
}
thank a lot.
