TMS570LC4357: EMIF clock for synchronous memories

Archana Rao

Intellectual 915 points

Part Number: TMS570LC4357

Hi,

EMIF_CLK for SDRAM is an output from microcontroller which is enabled when SDRAM CS is asserted.

Can this clock be made free running? Is there any register setting to do so?

Regards,

Archana Rao

over 6 years ago

0 QJ Wang over 6 years ago

TI__Guru**** 196306 points

Hello Archana,

There is no register to set EMIF_CLK free running. The EMIF outputs the clock only when there is transaction.

0 Archana Rao over 6 years ago in reply to QJ Wang

Intellectual 915 points

Hi Wang,

Thank you for your reply.

During asynchronous memory read/write access, is the internal EMIF_CLK also available on external pin?

We are interfacing this microcontroller with FPGA. Though we are operating in asynchronous mode, we are planning to connect EMIF_CLK to FPGA to avoid metastability at FPGA end.

Regards,

Archana Rao

0 Archana Rao over 6 years ago in reply to Archana Rao

Intellectual 915 points

Hi,

Any update on above request?

Regards,

Archana Rao

0 Archana Rao over 6 years ago in reply to Archana Rao

Intellectual 915 points

Hi,

Any update on above request?

Regards,

Archana Rao

0 QJ Wang over 6 years ago in reply to Archana Rao

TI__Guru**** 196306 points

Hi Archana,

Apologies for late response. The EMIF_CLK is free-running, and you can use this clock for FPGA. The EMIF_CLK is driven from VCLK3. You can configure ECLK to output VCLK3 at test clock mode, and use ECLK for your FPGA.

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TMS570LC4357: EMIF clock for synchronous memories