TMS570LS1227: Re-read the slave while the slave respond NAK for it need more time to process the request

Hi Sorry the configuration is as below. The previous mentioned  is not the correct one.

/** - i2c Enter reset */
i2cREG1->MDR = (uint32)((uint32)0U << 5U);

/** - set i2c mode */
i2cREG1->MDR = (uint32)((uint32)0U << 15U) /* nack mode */
| (uint32)((uint32)0 << 14U) /* free running */
| (uint32)(0U) /* start condition - master only */
| (uint32)((uint32)1U <<11U) /* stop condition */
| (uint32)((uint32)1U <<10U) /* Master/Slave mode */
| (uint32)((uint32)I2C_TRANSMITTER) /* Transmitter/receiver */
| (uint32)((uint32)I2C_7BIT_AMODE) /* xpanded address */
| (uint32)((uint32)0U << 7U) /* repeat mode */
| (uint32)((uint32)0U << 6U) /* digital loop back */
| (uint32)((uint32)0U << 4U) /* start byte - master only */
| (uint32)((uint32)0U << 3U) /* free data format */
| (uint32)(I2C_8_BIT); /* bit count */

/** - set i2c Backward Compatibility mode */
i2cREG1->EMDR = 0U;

/** - Disable DMA */
i2cREG1->DMACR = 0x00U;

/** - set i2c data count */
i2cREG1->CNT = 8U;

/** - disable all interrupts */
i2cREG1->IMR = 0x00U;

/** - set prescale */
i2cREG1->PSC = 10U;

/** - set clock rate */
i2cREG1->CKH = 36U;
i2cREG1->CKL = 36U;

/** - set i2c pins functional mode */
i2cREG1->PFNC = (0U);

/** - set i2c pins default output value */
i2cREG1->DOUT = (uint32)((uint32)0U << 1U) /* sda pin */
| (uint32)(0U); /* scl pin */

/** - set i2c pins output direction */
i2cREG1->DIR = (uint32)((uint32)0U << 1U) /* sda pin */
| (uint32)(0U); /* scl pin */

/** - set i2c pins open drain enable */
i2cREG1->PDR = (uint32)((uint32)0U << 1U) /* sda pin */
| (uint32)(0U); /* scl pin */

/** - set i2c pins pullup/pulldown enable */
i2cREG1->PDIS = (uint32)((uint32)0U << 1U) /* sda pin */
| (uint32)(0U); /* scl pin */

/** - set i2c pins pullup/pulldown select */
i2cREG1->PSEL = (uint32)((uint32)1U << 1U) /* sda pin */
| (uint32)(1U); /* scl pin */

/** - set interrupt enable */
i2cREG1->IMR = (uint32)((uint32)0U << 6U) /* Address as slave interrupt */
| (uint32)((uint32)0U << 5U) /* Stop Condition detect interrupt */
| (uint32)((uint32)0U << 4U) /* Transmit data ready interrupt */
| (uint32)((uint32)0U << 3U) /* Receive data ready interrupt */
| (uint32)((uint32)0U << 2U) /* Register Access ready interrupt */
| (uint32)((uint32)0U << 1U) /* No Acknowledgement interrupt */
| (uint32)((uint32)0U); /* Arbitration Lost interrupt */

/** - i2c Out of reset */
i2cREG1->MDR |= (uint32)I2C_RESET_OUT;

/** - initialize global transfer variables */
g_i2cTransfer_t.mode = (uint32)0U << 4U;
g_i2cTransfer_t.length = 0U;

Hi Wang,

Thanks for your reply. I have tried this.

If i ignore the NACK, because i set the count to 4 the master receives 0xFF+ACK, 0xFF+ACK, 0xFF+ACK, 0xFF+NACK.

Unless i check the receive data for correctness, i never know whether the received data is valid or 0xFF(wait signal from slave).

The way i need is if the slave respond NACK for the read, i need to read the next byte and if its 0xFF master should acknowledge and wait for 3 ms and reread until there is a ACK for the read. If slave acknowledge the read it will respond 04 00 03 40

How could we do this?

Thanks,

-Dinesh

How to send read command again if the slave responds NAK for the read?

In my case master pulls the SCL to low. I am trying to figure out how to send the read command  again.

-DInesh

Another information from is the clock stretching. The slave do the following,

"

The i2c chip can automatically pause bus transactions by holding the SCL line LOW on the I2C-bus when the device is
not ready for the next byte of data or prepare another byte to be transmitted. The Master wait for the SCL Line HIGH
before proceeding to the next byte

"

Will this be a clash while the master pull the scl low because of NACK from slave and slave pulled the line low as per above description?

-Dinesh

Hi Dinesh,

The slave supports clock stretch. Please check its communication protocol if it has a feature called acknowledge polling: in order for the master to know if the write is fully complete the master can issue an acknowledge polling command. If the device finishes the write then it will acknowledge.  If the device is still busy to complete the internal write cycle then it will return negative acknowledge. 

The slave device may have example code for master side to handle its clock stretch.

Hi Wang,

Thanks for your reply.

The slave data sheet only tells the following,

The i2c chip can automatically pause bus transactions by holding the SCL line LOW on the I2C-bus when the device is
not ready for the next byte of data or prepare another byte to be transmitted. The Master wait for the SCL Line HIGH
before proceeding to the next byte.

with RM=0, EMDR = 0, FDF = 0, 7bit addressing mode, Master keep the SCL low as soon as slave NACK for the read, from here, how to go on to send another read to the slave is what i am trying to figure out.

How to know whether the SCL is pulled down by master or slave, considering that could happen because of master pull low for NACK from slave or slave could stretch the scl low.

How to repeatedly read the slave until the slave ACK the read? And the re read should be done after master checking the SCL is high(Means released by Slave due to clock stretch).

I am kind of stuck here. You immediate support would help a lot.

Thanks,

Best Regards,

-Dinesh

Hi Dinesh,

Have you solved the slave clock stretch issue?