CCS/RM44L920: SPI receive overrun flag asserted using DMA in multi-buffer mode

user5890695

Part Number: RM44L920
Other Parts Discussed in Thread: HALCOGEN

Tool/software: Code Composer Studio

hi ,

Spi receive overrun flag always asserted when I used SPI to communicate with an external ADC using DMA in multi-buffer mode.

My SPI clock is 4MHz, and a single shot SPI DMA transmission which will transmitted 16 bytes between CPU and ADC is initiated in an timer interrupt routine.

The SPI DMA initialization follows examples "example_mibspiDMA.c" in examples folder of HalCoGen tool.

During my test, I found that RXOVRUNFLAG in SPIFLG register always be set and I wonder how does this happen?

I wonder if there is anything I missed?

Thanks,

Catherine

over 6 years ago

0 QJ Wang over 6 years ago

TI__Guru**** 198926 points

Hello Catherine,

The RXOVRN flag is set when a buffer in the RXRAM is overwritten by a new received word. While writing newly received data to a RXRAM location, if the RXEMPTY bit of the corresponding location is 0, then the RXOVR bit will be set to 1 during the write operation, so that the buffer starts to indicate an overrun. This RXOVR flag is also reflected in SPIFLG register as RXOVRNINTFLG and the corresponding vector number is updated in TGINTVECT0/TGINTVECT1 register.

Receiver overrun errors in multi-buffer mode can be completely avoided by using the SUSPEND until RXEMPTY feature, which can be programmed into each buffer of any TG.

You said ADC is initiated in timer ISR, Do you send commands to ADC through MibSPI? How do you configure the TX RAM and RXRAM?

0 user5890695 over 6 years ago in reply to QJ Wang

Prodigy 165 points

Hi QJ,

Thanks for your quick reply.

Yes, CPU will read out ADC sample data in timer ISR, and a ADC read command is transmitted before 3 clock command 0xFF.

So ADC access data register command followed by 3 clock command 0xff are configured into TX RAM with following routine:

void InitMultiBufferTxRam(mibspiRAM_t *spiRAM, uint32 *ptr, uint32 length)
{
uint32 i;
uint32 value;

    for ( i = 0 ; i < length; i++ )
    {
        value = *ptr;

        spiRAM->tx[i].control = (uint16)((uint16)4U << 13U) /* buffer mode */
                                | (uint16)((uint16) ( (value & SPI_CS_HOLD_MASK ) >> SPI_CS_HOLD_SHIFT ) << 12U) /* chip select hold */
                                | (uint16)((uint16)0U << 11U) /* lock transmission */
                                | (uint16)((uint16) ( (value & SPI_WDELAY_MASK) >> SPI_WDELAY_SHIFT ) << 10U) /* enable WDELAY */
                                | (uint16)((uint16)( (value & SPI_DFSEL_MASK) >> SPI_DFSEL_SHIFT ) << 8U) /* data format */
                                | (uint16)((value & SPI_CSNR_MASK) >> SPI_CSNR_SHIFT); /* chip select */

ptr++;
}

}

You mentioned that "Receiver overrun errors in multi-buffer mode can be completely avoided by using the SUSPEND until RXEMPTY feature, which can be programmed into each buffer of any TG."

I wonder if "SUSPEND" means that BUFMODE in TXRAM register should be configured as "suspend single-transfer mode(0x05)" instead of "continuous mode(0x04), which I am using and result in SPI receive overrun?

Best Regards,

Catherine

0 QJ Wang over 6 years ago in reply to user5890695

TI__Guru**** 198926 points

Hello Catherine,

The address of the overrun in RXRAM is indicated in this RXOVRN_BUF_ADDR register.

The SUSPEND is set in BUFMOD of TX RAM: suspend overwrite-protect mode. Suspend-to-wait until the corresponding RXEMPTY flag is set (the sequencer stops at the current buffer until the previously-received data is read by the host.

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CCS/RM44L920: SPI receive overrun flag asserted using DMA in multi-buffer mode