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RM48L952: Timing relationship between clock and control signals on the EMIF asynchronous interface.

John Gabler
Prodigy 20 points
Part Number: RM48L952

For the EMIF asynchronous interface, is there a defined timing relationship between the EMIF_CLOCK_OUTPUT and the EMIF control signals? I am interfacing to an FPGA and would like to make the memory interface synchronous.

  • 0
    TI__Guru**** 196566 points

    Hello John,

    The timing parameters are listed in Tables in datasheet (spns177d.pdf):

    1. Table 6-27: Data setup time, and data hold time.

    2. table 6-28:  other parameters

  • 0 in reply to QJ Wang
    Prodigy 20 points

    Thanks you for your quick response. The problem I am having is there is no relationship of the asynchronous bus's chip select, output enable, and read/write signals to any external clock. The microprocessor that is being replaced, defined the relationship between the input clock to the microprocessor and the bus signals. This allowed the FPGA interface to be synchronous to the microprocessor clock. In the RM48 there is no relationship of the bus signals and any external clock which will make the FPGA interface to be totally asynchronous. The design of an asynchronous interface is more complex and this would be a redesign of the currently implemented FPGA interface.

    .

  • 0 in reply to John Gabler
    TI__Guru**** 196566 points

    Hello John,

    There is no relationship to external clock.

  • 0 in reply to QJ Wang
    TI__Guru**** 196566 points

    Hello John,

    The EMIF control signals for async memory are driven by EMIF clock. Hercules MCU has one EMIF clock output, and you can use this clock for your FPGA.

  • 0 in reply to John Gabler
    TI__Mastermind 49120 points

    John,

    The EMIF_CLK signal is a free-running clock and is available as output once enabled. Note that this signal will have a delay through the output buffer in the part, which is not accounted for during the generation of the control signals as specified in the datasheet.

    Another possibility is to use the ECLK pin to output a desired clock frequency to the FPGA. The technical reference manual includes information on how to configure ECLK to output different clock domains / sources using the functional clock output mode or the clock test mode.

    Hope this helps.

    Regards, Sunil