TMS570LC4357: EMIF Refresh rates

Hello Tirumala,

There are 4 refresh urgency levels listed in Table 21-12 of the TRM:

1. Refresh May: backlog counter = 1-3
2. Refresh Release: backlog counter = 4-7
3. Refresh Need: backlog counter = 8-11
4. Refresh Must: backlog counter = 12-15

EMIF performs memory transactions according to the following priority (highest priority listed first):

1. If the EMIF's backlog refresh counter is at the Refresh Must urgency level, the EMIF performs multiple SDRAM auto refresh cycles until the Refresh Release urgency level is reached.
2. If an SDRAM read has been requested, the EMIF performs a read operation.
3. If the EMIF's backlog refresh counter is at the Refresh Need urgency level, the EMIF performs an SDRAM auto refresh cycle.
4. If an SDRAM write has been requested, the EMIF performs a write operation.
5. If the EMIF's backlog refresh counter is at the Refresh May or Refresh Release urgency level, the EMIF performs an SDRAM auto refresh cycle.
6. If the value of the SR bit in SDCR has been set to 1, the EMIF will enter the self-refresh state

After taking one of the actions listed above, the EMIF then returns to the top of the priority list to determine its next action. Because the EMIF does not issue auto-refresh cycles when in the self-refresh state, the above priority scheme does not apply when in self-refresh state.

Hi Wang,

So, it all depends on what rate core access devices connected through EMIF. Can we have some analysis with timing diagram on this?

Can you please confirm and provide your inputs Wang?

Hi,

In interfacing SDRAM to the controller, why should be the smaller value considered?. i.e. either  t_RAS or t_{REFRESH_RATE .}

Why can't the maximum value considered?

As given in sprugu6b(External Memory Interface).... in section 1.2.11

Thanks,

Tirumala Panguluri.

Hi,

It is mentioned that for the SDRAM, the AUTO REFRESH command is executed at least 4096 times for every Tref.

We are trying to interface SDRAM as well as asynchronous memory to the controller.

It is also mentioned that the stipulated period(trc) is required for a single refresh operation, and no other commands can be executed during this period.

Now when there is write operation to be done on the asynchronous memory, and the AUTO REFRESH command is given to SDRAM, how does it impact

the write operation on asynchronous memory? How many cycles does it take for AUTO REFRESH? How can we calculate the number of cycles for AUTO REFRESH?

Kindly provide this analysis with help of timing diagram. If possible please try to mention it with an example.

Thanks 

Tirumala