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TMS570LS3137: Details on L/P BIST tests

sreenivasan m
Genius 3705 points
Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Hi Team,

Can you please help in answering below questions:
1. Does Pbist self check or pbist/lbist tests performed during startup code generated from Halcogen is dependent on clock sources (number of clock sources and its configuration)?
2. The reason is that from the document, we understand that L/P BIST tests requires GCLK, HCLK and it can be either from PLL1 or PLL2. 

Please confirm, if use only one clock source say could be PLL2 and disable all other sources, will it impact P/L BIST tests?

  • 0
    Genius 3705 points

    Any updates on this?

  • 0
    TI__Guru**** 196226 points

    Hello,

    1. HCLK is required for LBIST and PBIST ROM, and VCLKx are required for peripheral RAMs.

       There are 6 clock sources: OSC, PLL1, PLL2, CLK80K, CLK10M, ExTCLKIN1, ExTCLKIN1. You don't have to enable all of them. The OSC, CLK80K, and CLK10M are enabled by default.

       For HCLK/VCLK, you can use any clock source to generate them. Normally I use PLL1.

    2. You are right. GCLK and HCK can be from either PLL1 or PLL2. If only PLL2 is used, you can disable PLL1. OSC, CLK80K, and CLK10M should not be disabled. CLK80K and CLK10M are used as reference clock for the crystal oscillator failure detection circuit.