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TMS570LC4357: EMIF auto refresh cycles

Tirumala
Prodigy 190 points

Part Number: TMS570LC4357

Hi,

It is mentioned that for the SDRAM, the AUTO REFRESH command is executed at least 4096 times for every Tref.

We are trying to interface SDRAM as well as asynchronous memory to the controller.

It is also mentioned that the stipulated period(trc) is required for a single refresh operation, and no other commands can be executed during this period.

Now when there is write operation to be done on the asynchronous memory, and the AUTO REFRESH command is given to SDRAM, how does it impact

the write operation on asynchronous memory? How many cycles does it take for AUTO REFRESH? How can we calculate the number of cycles for AUTO REFRESH?

Kindly provide this analysis with help of timing diagram.

Thanks 

Tirumala

  • 0
    TI__Guru**** 200246 points

    Hello Tirumala,

    The EMIF is able to interface with external SRAM, SDRAM, and asynchronous devices. The chip select 0 is dedicated for SDRAM, and chip select 2/3/4 are used for asynchronous devices. Only one chip select can be activated at a time.  

    If nCS[0] is enabled, the command and data are routed to SDRAM only. If nCS[2] is activated, the data is for the async device connected to mVS[2].

    The EMIF supports auto-refresh command that performs the refersh operation to one row in each memory bank simultaneously. The memory controller must issue a sufficient number (for example 4096) of auto-refresh commands every refresh interval (Tref=64ms is a common value). All banks must be idle when the auto-refresh command is issued.

    Please refer to 17.2.5.6.1 for calculation of RR. The number of cycles in a refresh interval for the SDRAM should be listed in SDRAM datasheet.