How to generate sine wave from HET/HTU?

Min J Park

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Tool/software: Code Composer Studio

Hello, I was trying to generage sine wave from HET/HTU with application note spna217.

I used launchpad xh2-570lc43(TMS570LC43). I got het pwm signal, but not sine wave.

Though I added sine_table buffer in CPU and transfer to HTU, I don't know how to go to next step - match sine_table with HET signal..

Is there anything I missed or Do I have to do other ways?

I'll add a picture and my project folder compressed.

Thank you.

8420.sine_wave_uart.tar.gz

over 7 years ago

0 Miro over 7 years ago

TI__Mastermind 21425 points

Hello,

Did you add low pass filter to your launchpad?

Best regards,
Miro

0 Min J Park over 7 years ago in reply to Miro

Prodigy 70 points

Yes, I added low pass filter with R=330, and C=0.1uF.

0 Min J Park over 7 years ago in reply to Min J Park

Prodigy 70 points

Now I deleted cache from Halcogen and changed MPU configuration - Region 1 type : NORMAL_OIWTNOWA_NOSHARED

and I got very interesting signal. I added a video.

What is this?! Is there some algorithm I have to add?

5518.20190705_101537.mp4

0 Miro over 7 years ago in reply to Min J Park

TI__Mastermind 21425 points

Hello,

It seems that the probe is connected before filter. Am I right?

Best regards,
Miro

0 Min J Park over 7 years ago in reply to Miro

Prodigy 70 points

Um, no, the probe is connected after filter.

0 QJ Wang over 7 years ago in reply to Min J Park

TI__Guru**** 201436 points

Hello,

Did you add any instruction to the NHET assembly code which will affect the IHADDR for HTU data transfer?

What is the PWM frequency? The cut-off frequency of your low-pass filter (330ohms, and 0.1uF) is 4.825khz.

0 Min J Park over 7 years ago in reply to QJ Wang

Prodigy 70 points

Hello

I didn't changed NHET assembly code except the PIN number.

The PWM frequency is 78.125kHZ (80MHz of VCLK2 divided SINE_FREQ_DIVIDER-16, and lr = 64/hr = 1).

Thank you.

0 QJ Wang over 7 years ago in reply to Min J Park

TI__Guru**** 201436 points

Hello,

I noticed that the lr in you configuration is still 128 rather than 64.

#define LRPFC 7

So you need to change the value in the following instruction to <<7:

sine_table[i] = (sine_table_percent[i] * (CNT_MAX_PERIOD << 6));

0 Min J Park over 7 years ago in reply to QJ Wang

Prodigy 70 points

Hello!

Yes, finally It did! Thanks a lot.

It is important to set the right value, and clear the cache.

The below picture is the 610Hz sine wave signal. I Set the values like that.

------------------------------------------------------------------------------------------------

1. halcogen -> VCLK = 80MHz, Loop time = 175ns(I think it's the last important..maybe I'm not sure)

2. ccs -> LRPFC = 6(to get 64 vclk2), SINE_FREQ_DIVIDER 16, SAMPLE_SIZE = 128

3. LPF -> I make a simple RC filter circuit- R = 1k, and C = 0.2uF(parallel with two of 0.1uF )

p.s. Also I chanced Write type-> NORMAL_OIWTNOWA_NONSHARED(write through, no write allocate, non shared)

I unchecked 'Enable Cache'... I don't know whether it is correct...

0 QJ Wang over 7 years ago in reply to Min J Park

TI__Guru**** 201436 points

Good job, Min. Thanks for updating.

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How to generate sine wave from HET/HTU?