TM4C1294KCPDT: How to set the V bit in xPSR register

Jay Wang_China

Prodigy 95 points

Part Number: TM4C1294KCPDT

Hi everyone:

I'm doing some design for CPU function test (the MCU is TM4C1294KCPDT), one of them is xPSR register test.

DB1 EQU 0x00
_DB1 EQU 0xFF

DB2 EQU 0x55
_DB2 EQU 0xAA

The following code could set N bit in xPSR

MOVS R0, #DB1
CMP R0, #_DB1
BPL Check_Error
BEQ Check_Pass

The following code could set Z bit in xPSR

MOVS R0, #DB1
CMP R0, #DB1
BGT Check_Error
BEQ Check_Pass

The following code could set C bit in xPSR

MOVS R0, #DB1
CMN R0, #DB1
MOVS R0, #DB2
CMP R0, #DB2
BCC Check_Error
BEQ Check_Pass

but I have no idea how to set the V bit, the V bit means overflow flag

I use 0x7f + 0x1 = to produce carry bit, but V bit still remains 0.

It is very kind of you-all if you have any ideas, thank u.

over 6 years ago

0 Bob Crosby over 6 years ago

TI__Guru 72500 points

The overflow flag is set when doing signed arithmetic the result cannot be represented as the signed two's complement in the width of the ALU (arithmetic logic unit). The Cortex M4 processor has a 32-bit wide ALU. When you add 0x40000000 + 0x40000000, the result is 0x80000000. But on a 32-bit machine, 0x80000000 in 2's complement is a negative number (-2147483648). You added two positive numbers and got a "negative" result. The V bit will be set. (Likewise, when you add two negative numbers and get a positive result, the V bit is also set.)