Compiler/TMS570LS0432: #define NERROR_HOLD_DELAY (uint32)0u

Hello Whong,

This is the delay counter used before clearing nERROR. NERROR_HOLD_DELAY is defined as 10 in V2.3.1, and 0 in V2.4.0.

The ESMEPSR register provides the current ERROR status. Once an error occurs, the ESM module drives the nERROR pin low and the ESMEPSR is cleared. A power on reset or a write of 0x5 to ESMEKR is required to release the ESM error pin back to normal state. Once the nERROR pin is driven low, it remains in this state for the time specified by the Low-Time Counter Preload register (LTCPR).

My understanding is that NERROR_HOLD_DELAY can be any value. This loop is not required before issuing 0x5 to ESK register.

Yes, it is a delay value. Actually this is not required.