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TMDX570LC43HDK: SCI loopback DMA data retrieval

Part Number: TMDX570LC43HDK
Other Parts Discussed in Thread: HALCOGEN

Dear all, I am currently modifying the SCI loopback DMA example to link the data transfer to a physical button on the dev board. The behaviour is as expected, when i press the button 8 times the exception is triggered as configured in the DMA control packet. The problem comes when I try to real RX_DATA inside the ISR, it is set to all zeroes, but i can see before triggering that the data are actually being written there. I am not an expert on this board/processors, so i might have been missing something or this is not the correct way to retrieve data. I attach my main function code, the project was generated by Halcogen 4.7.1 and developed in CCS Version: 7.4.0.00015 

/** @file HL_sys_main.c 
 *   @brief Application main file
 *   @date 11-Dec-2018
 *   @version 04.07.01
 *
 *   This file contains an empty main function,
 *   which can be used for the application.
 */

/* 
 * Copyright (C) 2009-2018 Texas Instruments Incorporated - www.ti.com
 *
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 */

/* USER CODE BEGIN (0) */
/* USER CODE END */

/* Include Files */

#include "HL_sys_common.h"

/* USER CODE BEGIN (1) */
#include "HL_system.h"
#include "stdio.h"
#include "HL_gio.h"
#include "HL_sci.h"
#include "HL_sys_dma.h"
/* USER CODE END */

/** @fn void main(void)
 *   @brief Application main function
 *   @note This function is empty by default.
 *
 *   This function is called after startup.
 *   The user can use this function to implement the application.
 */

/* USER CODE BEGIN (2) */
#define size 8
/* External connection (SCI3 TX -> SCI4 RX) is needed in case LOOPBACKMODE is defined as 0 */
#define LOOPBACKMODE 1
/* Rx data buffer */
uint8_t RX_DATA[size] = { 0 };
/* Addresses of SCI 8-bit TX/Rx data */
#if ((__little_endian__ == 1) || (__LITTLE_ENDIAN__ == 1))
#define SCI3_TX_ADDR ((uint32_t)(&(sciREG3->TD)))
#define SCI3_RX_ADDR ((uint32_t)(&(sciREG3->RD)))
#define SCI4_TX_ADDR ((uint32_t)(&(sciREG4->TD)))
#define SCI4_RX_ADDR ((uint32_t)(&(sciREG4->RD)))
#else
#define SCI3_TX_ADDR ((uint32_t)(&(sciREG3->TD)) + 3)
#define SCI3_RX_ADDR ((uint32_t)(&(sciREG3->RD)) + 3)
#define SCI4_TX_ADDR ((uint32_t)(&(sciREG4->TD)) + 3)
#define SCI4_RX_ADDR ((uint32_t)(&(sciREG4->RD)) + 3)
#endif

#define DMA_SCI3_TX  DMA_REQ31
#define DMA_SCI3_RX  DMA_REQ30
#define DMA_SCI4_TX  DMA_REQ43
#define DMA_SCI4_RX  DMA_REQ42

#define SCI_SET_TX_DMA      (1<<16)
#define SCI_SET_RX_DMA      (1<<17)
#define SCI_SET_RX_DMA_ALL  (1<<18)
/* USER CODE END */

int main(void)
{
    /* USER CODE BEGIN (3) */
    //uint32 sciTxData, sciRxData;
    uint32 sciRxData;
    //g_dmaCTRL g_dmaCTRLPKT1, g_dmaCTRLPKT2;
    g_dmaCTRL g_dmaCTRLPKT2;
    gioInit();
    sciInit();

#if LOOPBACKMODE == 1
    /* Enable SCI loopback */
    sciEnableLoopback(sciREG3, Digital_Lbk);
    while (((sciREG3->FLR & SCI_TX_INT) == 0U) || ((sciREG3->FLR & 0x4) == 0x4))
    {
    } /* Wait */

    /*Assign DMA request SCI3 receive to Channel 1*/
    dmaReqAssign(DMA_CH1, DMA_SCI3_RX);

    sciRxData = SCI3_RX_ADDR;

#else
    while (((sciREG3->FLR & SCI_TX_INT) == 0U) || ((sciREG3->FLR & 0x4) == 0x4))
    {
    } /* Wait */

    /*Assign DMA request SCI3 transmit to Channel 0*/
    //dmaReqAssign(DMA_CH0, DMA_SCI3_TX);
    /*Assign DMA request SCI4 receive to Channel 1*/
    dmaReqAssign(DMA_CH1, DMA_SCI4_RX);

    sciTxData = SCI3_TX_ADDR;
    sciRxData = SCI4_RX_ADDR;

#endif
    /*Configure control packet for Channel 1*/
    g_dmaCTRLPKT2.SADD = sciRxData; /* source address             */
    g_dmaCTRLPKT2.DADD = (uint32_t) RX_DATA; /* destination  addr ss       */
    g_dmaCTRLPKT2.CHCTRL = 0; /* channel control            */
    g_dmaCTRLPKT2.FRCNT = size; /* frame count                */
    g_dmaCTRLPKT2.ELCNT = 1; /* element count              */
    g_dmaCTRLPKT2.ELDOFFSET = 0; /* element destination offset */
    g_dmaCTRLPKT2.ELSOFFSET = 0; /* element destination offset */
    g_dmaCTRLPKT2.FRDOFFSET = 0; /* frame destination offset   */
    g_dmaCTRLPKT2.FRSOFFSET = 0; /* frame destination offset   */
    g_dmaCTRLPKT2.PORTASGN = PORTB_READ_PORTA_WRITE;
    g_dmaCTRLPKT2.RDSIZE = ACCESS_8_BIT; /* read size                  */
    g_dmaCTRLPKT2.WRSIZE = ACCESS_8_BIT; /* write size                 */
    g_dmaCTRLPKT2.TTYPE = FRAME_TRANSFER; /* transfer type              */
    g_dmaCTRLPKT2.ADDMODERD = ADDR_FIXED; /* address mode read          */
    g_dmaCTRLPKT2.ADDMODEWR = ADDR_INC1; /* address mode write         */
    g_dmaCTRLPKT2.AUTOINIT = AUTOINIT_OFF; /* autoinit                   */

    /*Set control packet for channel 0 and 1*/
//    dmaSetCtrlPacket(DMA_CH0, g_dmaCTRLPKT1);
    dmaSetCtrlPacket(DMA_CH1, g_dmaCTRLPKT2);

    /*Set dma channel 0 and 1 to trigger on hardware request*/
//    dmaSetChEnable(DMA_CH0, DMA_HW);
    dmaSetChEnable(DMA_CH1, DMA_HW);

    /*Enable DMA*/
    dmaEnable();
    dmaEnableInterrupt(DMA_CH1, BTC, DMA_INTA);
    /*Enable button for GioA 7*/
    gioEnableNotification(gioPORTA, 7);

#if LOOPBACKMODE == 1
    /*Enable SCI3 Receive DMA Request*/
    sciREG3->SETINT |= SCI_SET_RX_DMA | SCI_SET_RX_DMA_ALL;

#else
    /*Enable SCI3 Transmit and SCI4 Receive DMA Request*/
    sciREG3->SETINT |= SCI_SET_TX_DMA;
    sciREG4->SETINT |= SCI_SET_RX_DMA | SCI_SET_RX_DMA_ALL;
#endif
    _enable_IRQ();
    while (1)
        ;
    /* USER CODE END */

    return 0;
}

/* USER CODE BEGIN (4) */
uint8 buffer[1];
uint8 incrementalT = 'a';
int vecesBoton = 0;
int i = 0;
void gioNotification(gioPORT_t *port, uint32 bit)
{
    buffer[0] = incrementalT;
    sciSend(sciREG3, 1, buffer);
    incrementalT++;
    vecesBoton++;
}
int incrementalR = 0;
void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel)
{
    incrementalR++;
    dmaSetChEnable(DMA_CH1, DMA_HW);
}
/* USER CODE END */

Best Regards

  • Hello,

    Do you enabled the MCU cache? If Yes, did you change SRAM to be write-through like here:

    Since DMA_CH1 is already set to use hardware request you don't have to set this again in dmaGroupNotification. Also, control packet is set in a way DMA will transfer 8 bytes. More details on DMA configuration can be found in chapter 20 of device TRM and for SCI using DMA in Section 30.4 of device TRM.

    Best regards,
    Miro

  • Thanks, enabling the MCU cache fixed my problems.

    I mark the thread as solved.