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TMS570LS3137: TMS570LS3137 CPU RAM test

Kalyan Vagvala61
Expert 1075 points

Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Hi,

I am trying to implement timeout in HALCOGEN generated startup code for TMS570LS3137 based hardware. Below the while loop from afterSTC() i am referring:

pbistRun(0x08300020U, /* ESRAM Single Port PBIST */
(uint32)PBIST_March13N_SP);

/* Wait for PBIST for CPU RAM to be completed */
/*SAFETYMCUSW 28 D MR:NA <APPROVED> "Hardware status bit read check" */
while(pbistIsTestCompleted() != TRUE)
{
}/* Wait */

I initialized RTI module before CPU RAM test and tried reading RTI register value to implement timeout, but the execution is getting stuck in the timeout calculation. Reading RTI registers always reads the same value but i could see RTI register contents incrementing as expected. Can you please help me to understand this?

By the time CPU RAM is tested Initialization of copy table, global variables, and constructors not happened, i am using MIBSPI RAM to store the RTI register values.

Thanks,

Kalyan

  • 0
    TI__Guru**** 199236 points

    Hello Kalyan,

    The up counters are implemented as shadow registers. Reading RTIUCx without having read RTIFRCx first will return always the same value. RTIUCx will only be updated when RTIFRCx is read.

    The right reading sequence should be:

    The free running counter (RTIFRCx) must be read first. This priority will ensure that in the cycle when the CPU reads RTIFRCx, the up counter value is stored in its counter register (RTIUCx). The second read has to access the up counter register (RTIUCx), which then holds the value which corresponds to the number of RTICLK cycles that have elapsed at the time reading the free running counter register (RTIFRCx).

  • 0 in reply to QJ Wang
    Expert 1075 points

    Hi Wang,

    Thanks for your response. i will try the suggestion and get back if any issue.

    Thanks,

    Kalyan