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TM4C1294NCPDT: Could this cause the micro to latch up ?

David Chance
Genius 4785 points

Part Number: TM4C1294NCPDT

In one of my prototype, after flashing in the codes, the micro gets burning hot when I try to debug it via JTAG, and I try to find out the reason.

In this design, the micro is powered by normal power and backed up by supercaps. When the normal power is removed, the Vcc will be supplied by supercaps and gradually drop from 3.3V to  0 within 10 seconds. If XDS100v3 is connected to the JTAG port of the micro, it may still try to communicate with the micro, so the voltage on JTAG lines are higher than "Vcc" of the micro, would this post a problem to the micro?

  • 0
    TI__Guru 72500 points

    Driving an input pin to a voltage higher than Vdd on this device is never a good idea. The JTAG pins are diode clamped to Vdd. You need to limit the injection current to 2mA or less. 

  • 0 in reply to Bob Crosby
    Guru 117855 points

    Bob,

    Kudos to you on such a 'well documented' response to poster David.

    That chart (especially the parameter notations) is most valuable & should be appreciated.    

    With that said - during my  (past) 'tour' at another Giant Semi Firm - we produced similar charts - and discovered that,  'Excessive time of exposure' of I/O Pads to (even) 'w/in Spec voltage and/or current levels'  while the MCU was 'Non-Powered' - (likely) raised the prospect of the MCU's (early) failure!

    Many such tests are performed while the devices are, 'On the Wafer' - and  (Time) is 'OF THE ESSENCE!'   In such a case - the detection of such a 'time-related/triggered weakening' - is likely to pass 'without note!'