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TMS570LC4357: Need to use DMA for handling data over peripherals

sreenivasan m
Genius 3705 points
Part Number: TMS570LC4357

Hi Team,

We would like to use DMA in chain mode for handling data over SPI interface such that after receiving 10 bytes of data by channel (1), it should trigger other DMA channel (2) to receive the data over SPI and should trigger channel 1 again and this should continue.

Please find the code in attachment where DMA is enabled with chain mode to handle it, but it looks like we only end up on receiving data in one channel.

We tried to enable DMA for both channels (as it will be processed CH0 and then CH1), in this case, nothing is received on channel 2 desitnation and for channel 1 destination, single packet is copied.

Can you please look into this and let me know if we can use chain mode of DMA for handling peripheral traffic?

  • 0 in reply to sreenivasan m
    Genius 3705 points

    Any updates on this?

  • 0 in reply to sreenivasan m
    Genius 3705 points

    Hi Team,

    Below things also tried. Configured DMA channel 0 only with frame size 10, element count is 1. Enabled interrupts for half block transfer and could see that interrupt is received, but DMA channel pending register shows 1 even though we didnt configured it. Can you explain this behaviour.

    Also, how to continue execution after receiving the interrupt.

    Tried below things during the interrupt service routine:

    1. Enabled DMAREQ in SPIINT0 register, but still it is not working.

    Can you please look into this and provide your inputs sooner?

  • 0 in reply to sreenivasan m
    TI__Guru**** 196566 points

    Hello,

    The code you attached doesn't enable the DMA channel chaining. Channel chaining can be used to trigger multiple channels without an external DMA request. If DMA channel 0 is for SPI RX, and DMA channel 3 is for data copy from SDRAM to SRAM, channel 3 can be triggered by the SPI RX DMA request. The order of channels services is Channle1-->Channel3. The only thing you need to do is to write channel3+1 to CHAIN field of CHCTRL register.

  • 0 in reply to QJ Wang
    Expert 1355 points

    Hi,

    I tried with configuring the channel 1 as first reception and the channel 4 as the second reception packet. but it is not at all receiving the data.

    as configuring the channel 1 i have provided the value as 4 in CHCTRL field. but it didn't work.

    In this case How can we resume the data reception for the 3rd channel?

    I have also observed that, after the interrupt occurs for the half block transfer completion, the further transmission data is not even going in the SPI Buffers.

    But if in the interrupt handler when i disable the interrupt it starts receiving the data but not transfer the control to the other channel.

    Can you please assist me with this DMA behaviour?

    Regards,

    Shivam Kakad

  • 0 in reply to QJ Wang
    TI__Guru**** 196566 points

    Each time a DMA request is made, either one frame transfer or one block transfer can be chosen. An active DMA request signal will trigger a DMA transaction. When a HW request is generated, the DMA Status Register is set, and PEND register is set as well. One the pending register is set, it remains set even if the corresponding channel is disabled. It is cleared at the end of a frame or a block transfer, or after bus error occurs, or when the control packet is modified.

    If ONESHOT bit in DMACTRL register is set, only ICOUNT+1 transfers are performed.

  • 0 in reply to QJ Wang
    Genius 3705 points

    Hi Wang,

    Can you please share a sample code to use chain mode of transfer for SPI traffic which would help us? Also, please do share us the steps to be implemented when we receive BLock or Half block DMA transfer interrupts. 

  • 0 in reply to sreenivasan m
    Genius 3705 points

    Also, we are not using MibSPI, instead using SPI. So, still DMAXCTLR register is applicable here?

  • 0 in reply to sreenivasan m
    Genius 3705 points

    Please let me know if you have any updates on this.

  • 0 in reply to sreenivasan m
    TI__Guru**** 196566 points

    Hello,

    DMAXCTLR is to enable the DMA for MibSPI. The DMAREQEN SPIINT0 register is for SPI compatible mode. The DMA channel chaining should work if the DMA packets are configured properly.

    If your project doesn't work, please post your project, so I can take a look. The code you posted before does not enable the DMA channel chaining.