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CCS/TMS570LC4357: Issue for setting the bit SWCHENAS for the DMA

Shivam Kakad
Expert 1355 points

Part Number: TMS570LC4357

Tool/software: Code Composer Studio

Hi,

I am working on the SPI-DMA Communication. in the hardware triggering method i could able to set the HWCHENAS bit for the respective channel, but facing the issue for the SWCHENAS. 

Here i have attached the snapshot for the same.

Here you can see, though after the execution for enabling the channel for the SW trigger, still the bit is not setting it up.

where dmaSetChEnable() defined as:

if(type == DMA_HW)
{
dmaREG->HWCHENAS = (uint32)1U << channel;
}
else
{
dmaREG->SWCHENAS = (uint32)1U << channel;
}

Please help me in this issue.

Reagrds,

Shivam Kakad.

  • 0
    TI__Guru**** 201476 points

    Hello Shivam,

    The SWCHENA bit is automatically cleared when:

    1. A bus error is detected (BERFLG register)

    2. A transaction parity error occurs

  • 0 in reply to QJ Wang
    Expert 1355 points

    Hi Wang,

    Would like to understand how DMA with SW and HW trigger works during Transmission when configured it in Slave mode.

    Please note that its for SPI mode only not on MibSPI.

  • 0 in reply to Shivam Kakad
    Expert 1355 points

    Hi,

    Can anybody please help me in solving this issue?

    Regards,

    Shivam Kakad

  • 0 in reply to Shivam Kakad
    Expert 1355 points

    Hi Wang,

    During this Process i can see the TEREvtCtrl register is reading the data as Ah.

    It means that transaction error event has occured, how can i get away with it?

    Can you please explain me what all are the steps needed to work with SW triggering? as it is working with the HW triggering method for me but not for the SW.

    Please assist me in this issue.

    Regards,

    Shivam Kakad

  • 0 in reply to Shivam Kakad
    TI__Guru**** 201476 points

    Hi Shivam,

    In receive side, you can use either HW trigger or SW trigger. I prefer to use HW trigger:

    1. DMA request is generated when the received data in RX shift register is directly copied into SPIBUF if both SPIBUF and RXBUF are empty.

    2. DMA request is generated when the RX shift register contents is copied to RXBUF If SPIBUF is already full at the end of receive completion.

    For using SW trigger, after getting the RX interrupt, call the enableDMA() API to read the data.