Analog input Resistance2

Quickly - follows a 'few comments' - which may warrant your consideration:    Note: content w/in this post proves FAR from 'Support Team.'

• Achieving '12 bit Analog Signal Resolution'  - over a '32V signal span'  (can you say 'enormous') - is a (highly) demanding & challenging task!
• The majority of the MCUs here (and elsewhere) 'confine and/or contain' their Analog Signal Input Span to 3V3.   (3.3V)
• As applying voltage beyond the MCU's (or independent ADC IC's) spec proves destructive - you must (significantly) reduce your input signal.
• To comply w/the MCU or dedicated ADC's signal restriction - one (usually) creates a (near) 10:1 voltage divider.   In so doing - your signal-span is reduced to a 'safe' 3V2.
• That said - there IS a severe 'Down-Side' - and that is the Amplitude LOSS of  ~90% of your original signal.

In light of the above:

• What do you believe that 'signal reduction' - can (or will) do - to your quest for '12 bit resolution?'
• Same for  ±1% FS

Our small group is curious as to how such a 'specification' was created?    How were these parameters chosen?    Is there a 'past record' of similar design work - to 'fall back upon?'

My group's preference (hopefully clear now) is to 'Guide You' to a solution ... Never to 'Provide a Cut/Paste - User Effort-Lite'  - (cough) 'solution.'    Only 'one' of those approaches 'Teaches - and Lasts!'

Hi Team,

It is challenging task.The signal before reaching MCU to be reduced 3.3V .The question was mainly about how we can achieve input resistance of 50.7 kΩ (0...32 V) .Can it be done with simple voltage divider circuit or a amplifier is required?

Thanks and Regards,

Prima Rodrigues

May a (most unlikely) 'team' still respond?

How would one know that the 'input resistance' (alone) was your major objective?    And - if the 'basic design objectives' are 'flawed' - as we believe  is the case  - what IS the value of  'input resistance.'

Would you be so good as to 're-read' the answering post.   (it was systematically expanded - due to 'Storm power issues' impacting our Chicago Office Tower.)

My group would ALWAYS employ an Amplifier.    The flexibility and 'MCU protective role' - both provided by the 'front-end amplifier'  -  make its choice a, 'No Brainer.'

May an opposing viewpoint be offered?

Now the poster specified a 'resolution of 12 bits - and that to be maintained - over a 32V signal input span.    Somehow - to (both) the poster - and to this reporter - such DOES appear to 'challenge.'

Facts should replace opinion - don't you agree?   Thus:

• Assume a 12 bit ADC (as only those are resident, this forum) - which spans 0-3V3.   We then would have 3300mV/4096 = 0.806mV/ADC Count.    And checking - 0.806mV * 4096 = 3300mV
• Now examine the (same) 12 bit ADC spanning 0-10V.   The (now necessary) voltage divider has the ratio 10:3.3: or 3.03.   And 10,000mV/4096 = 2.441mV/ADC Count.    Has the suggested 'voltage divider' not (clearly) degraded input signal resolution?   (thus challenging!)
• And now 12 bit ADC spanning (poster's) 0-32V.   Voltage divider has the ratio  32:3.3 or 9.697.    And 32,000mV/4096 = 7.813mV/ADC Count.

Thus - has the goal of  '12 bit resolution - achieved over (so wide) an input signal span' - been achieved?    My group believes NOT - thus 'challenge' has indeed - been established.    As a matter of fact - the critical input signal (mV/ADC Count) resolution has been degraded by (nearly) a factor of ten!      (0.806 vs. 7.813, 'mV/ADC Count')

It would appear then - that an ADC able to resolve 'beyond 12 bits' would be required - to meet poster's (stated, 12 bit) objective!    (That due to the voltage divider's (absorbing) excess signal.)    

As noted (and documented herein) - that voltage divider 'extracts some cost!'

To poster's  2nd 'design goal'  - "1% FS accuracy" - with 32,000mV as 'FS (full-scale)' - that's  calculated  (via a 2 decimal point shift (left)) - yielding,  '320mV.'    And even w/the 'challenge' of maintaining 12 bit resolution - over 'so wide' a signal span - meeting that '320mV'  accuracy objective - appears achievable.

[edit]... 'So strange - the quiet!'   While surely the case has been made re: 12 bit ADC being (w/out doubt) 'Over-Challenged' - what resolution ADC must be deployed - as a 'valid' replacement.  (for the over-challenged - 12 bit ADC - which 'lurks' here.)   Consider that each 'Added Bit of ADC Resolution' DOUBLES its (potential) resolution.   (all major design parameters/capabilities being equal)   Now our poster suffers (nearly) a 'Factor of TEN' resolution LOSS!    (that due to the imposition of the voltage follower)  To maintain the poster 'specified' 12 bit resolution - the 'Candidate ADC' must be capable of meeting (or besting) the earlier described (via calculation) 0.806mV/ADC Count.   Proposed then is a '16 bit ADC' - which reveals:  32,000mV/65,536 = 0.488mV/ADC Count.    Note too - this performance level 'exceeds' poster's specification - AND is readily available (& via multiple sources!)    A '15 bit ADC' would land 'just outside' poster's spec (0.976mV/ADC Count) yet is (highly) non-standard... 

Is it possible - that just maybe - due to the 'thought, effort, & 'interlocked' detail presented herein' - that poster's specification 'Challenge' - has been met?

And 'where IS the *** LIKE ***'  is it not 'so very deserved?'

Thank you - we must  then, 'Agree to Disagree.'

We meet here as 'friends' - yet somehow - have descended into dilemma.     Have we not - an almost sure - 'Chicken vs. Egg' scenario?     One believes that the Resolution must dominate - the other that the 'ADC's Step Signal Recognition' (usually expressed in mV/µV per ADC Step) leads the action.    Which is (most) correct - can even (both) be correct?   (Might 'challenge' have (finally) arrived?)

Have you not - in your attempt to promote 'Resolution - and only Resolution' created a 'False Equivalency' between Resolution and the  FAR MORE CRUCIAL 'mV/µV per ADC STEP?'    Does not your 'acceptance (even welcoming)' of ANY 'mV/µV per ADC STEP' present an 'Unmanaged & Sliding Target?'    Surely the voltage divider causes  HIGHLY KNOWN DEGRADATION to the ADC's 'Recognition of Voltage Level Steps' - and that is 'Far from desirable!'     Can this much - be agreed?

Is it not 'normal/customary'  for  many/most  such Analog Designs to  focus FIRST upon accuracy - and (only)  AFTER  that  accuracy target is known/declared - is the 'Required Resolution of the ADC' - calculated & specified!       Indeed - 'Resolution by itself' - proves (essentially) (pardon) meaningless - it is the 'Stepped Voltage Level' which the ADC can resolve - which proves VITAL!    And is usually the 'First Order' of ADC Selection business!

Note too - as my team expects that you know - such 'Increased (High) Resolution ADCs' - often are chosen (perhaps primarily chosen) for their accommodation of 'Wide & Dynamic Input signal range' - and not so much - for their (extreme) accuracy.    But for the sake of  (your) argument - the higher resolution ADC (i.e. the 16 bit - earlier recommended) stands clearly (to my team's mind) as  the 'Device of Choice' in this application!

There ARE alternative methods - which replace the voltage divider - yet those prove (even more challenging) - and 'challenge' has been 'removed' from this 'field of play.'    (one simple means sees the bottom leg of the resistor divider 'dynamically switched among different value resistors' - based upon the input signal's 'Pre-Divider' voltage level.   My firm employs this as well as several 'more intense & innovative' (voltage divider replacement) means/methods' - in our submersible & autonomous vehicle development.    (I past co-founded, served as VP Engineering - and then took that Tech Firm Public - via (just) such 'innovative, even inspired techniques.')     Even though - especially though - (others) may have disagreed!

Best of luck to you & our (long silent) poster.   My group remains (highly doubtful) that  poster's spec was (carefully) devised, weighed & considered...   My writing here intends to, 'Inform & Advise' - is believed to be adequately detailed/justified - and may - or may not - be accepted...