Hi,
I have a question for Errata L2FMC#5.
According to the description, if an instruction address bits [21:5] are equal to the target memory location address bit [21:5],
the data read is the instruction itself instead of actual data located at the target address.
Q1) Is there any way to confirm L2FMC#5 happened?
I think applying workaround and check if it works is one method.
Do we have any other ways (checking status register, etc.)?
Q2) Suppose data are read first (prefetched in pipeline) then an instruction located at address bits[21:5] equal to the data address bits [21:5] is executed.
Does the similar issue happen?
(i.e. an instruction fetched is not the actual instruction at the address, but the data previously pipelined.)
Thanks and regards,
Koichiro Tashiro