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TMS570LS3137: cpuSelfTest Query

Kalyan Vagvala61
Expert 1075 points
Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Hello,

Can you please help me get answers for below listed question related to cpuSelfTest(); generated by HALCOGEN version 4.7:

1. Why the cpuSelfTest() function not setting STCCLKDIV[26:24] = 1 as suggested in Section 8.5.1 of SPNU499C?

2. We are configuring VCLK as 20 MHZ, Can i get the STC test duration with HCLK = 180 MHZ and VCLK = 90MHz? It would be good if we have a equation based on the HCLK/VCLK ratio.

3. When i configure HCLK = 180 MHZ, VCLK = 90 MHZ, STCCLK = 90MHZ, stcREG->STCTPR = 0x0x8019UL (which is 364 usec as per TRM); cpuSelfTest() fails in this case. why is that what would be the good tolerance value?

Please point me to any document where i can get above details.

Thanks,

Kalyan

  • 0
    TI__Guru**** 199096 points

    Hello Kalyan,

    1. STCCLK determines the self-test execution speed. STC clock divider (STCCLKDIV) is 0x0 by default: STC clock is HCLK divided by 1.

    2. STCCLK is driven from HCLK rather than VCLK. STCCLK=HCLK/(STCCLKDIV+1). The VCLK dividers are defined in CLKCNTL and CLKCNTL2 registers. 

    3. Can you try a larger time-out value?